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| publication release date: may, 2007 revision 1.3 - 1 - W681307 product datasheet usb1.1 codec microprocessor control unit with 32kb mask rom and 4kb ram.
W681307 publication release date: may, 2007 revision 1.3 - 2 - amendment history ver date filename author changes ( ? : modified, ? : added, : removed) reference 1.0 2006/11/22 W681307_data sheet_v1.0 mcsu 1.1 2006/12/02 W681307_data sheet_v1.1 mcsu ? modify register 0x14c4. ? modify figure 14-2. W681307_data sheet_v1.0 1.2 2006/12/28 W681307_data sheet_v1.2 mcsu ? modify register 0x14e5. W681307_data sheet_v1.1 1.3 2007/07/23 W681307_data sheet_v1.3 tychiu ? modify endpoint table 18.2.1. W681307_data sheet_v1.2 W681307 publication release date: may, 2007 revision 1.3 - 3 - contents 1. general description ................................................... .................................................. - 9 - 2. features ................................................... ................................................... ..................... - 10 - 3. pin configuration ................................................... ................................................... . - 11 - 4. pins description ................................................... ................................................... ...... - 12 - 5. system diagram ................................................... ................................................... ....... - 17 - 5.1 function block diagram ................................................... ................................................ - 1 7 - 5.2 i/o cells in winbond mcu chip ................................................... ................................. - 18 - 6. electrical characteristics ................................................... .................................. - 20 - 6.1 absolute maximum ratings ................................................... .......................................... - 20 - 6.2 dc characteristics ................................................... ................................................... ...... - 20 - 6.3 analog transmission characteristics ................................................... ............................ - 21 - 6.3.1 amplitude response for analog transmission performa nce ....................................... - 21 - 6.3.2 distortion characteristics for analog transmission performance ................................ - 21 - 6.4 analog electrical characteristics ................................................... ................................... - 22 - 6.5 power drivers ? po1, 2 ................................................... ................................................. - 22 - 6.6 programmable output linear regulator ................................................... ....................... - 23 - 6.7 usb phy electronic characteristics ( 25c, vdd_usb = 3.3v, dvdd1, 3 =1.9v) ............. - 23 - 6.8 usb pll electronic characteristics ( 25c, avdd = 3 .3v, dvdd1, 3 =1.9v) .................... - 24 - 6.9 the crystal specification requirement ................................................... .......................... - 24 - 6.10 recommended crystal specification ................................................... ............................. - 25 - 7. memory and register map ................................................... ...................................... - 26 - 7.1 program memory map ................................................... .................................................. - 26 - 7.2 data memory map ................................................... ................................................... ..... - 26 - 7.3 register map ................................................... ................................................... .............. - 27 - 7.3.1 mixer and speech logic registers overview ................................................... ............ - 27 - 7.3.2 support logic registers overview ................................................... ............................ - 27 - 7.3.3 interface logic registers overview ................................................... ........................... - 28 - 7.3.4 speech interface registers overview ................................................... ........................ - 28 - 7.3.5 processor interface registers overview ................................................... .................... - 29 - 7.3.6 transcoder dsp registers overview ................................................... ......................... - 29 - 7.3.7 echo canceller registers overview ................................................... .......................... - 30 - 7.3.8 soft clip registers overview ................................................... .................................... - 31 - 7.3.9 codec digital part ................................................... .................................................. - 31 - 7.3.10 sounder path select ................................................... .................................................. - 31 - 7.3.11 frequency adjustment of crystal oscillator ................................................... ............. - 31 - 7.3.12 specific register ................................................... ................................................... ..... - 31 - 7.3.13 vag selection ................................................... ................................................... ....... - 32 - 7.3.14 codec control register overview ................................................... .......................... - 32 - 7.3.15 specific registers ................................................... ................................................... ... - 32 - 7.3.16 test cases and debugging registers overview ................................................... ........ - 32 - 7.3.17 charge park detection ................................................... .............................................. - 32 - 7.3.18 da high pass filter selection ................................................... ................................... - 33 - 7.3.19 ti path selection ................................................... ................................................... . - 34 - 7.3.20 network side / acoustic side power measurement ................................................... .. - 34 - 7.3.21 pcm highway channel registers overview ................................................... ............ - 35 - 7.3.22 spi interface registers overview ................................................... .............................. - 35 - 7.3.23 data flash spi interface registers overview ................................................... ............. - 36 - W681307 publication release date: may, 2007 revision 1.3 - 4 - 7.3.24 w2s interface registers overview ................................................... ............................ - 36 - 7.3.25 usb control registers overview ................................................... .............................. - 37 - 7.3.26 isp mode ................................................... ................................................... ............... - 38 - 8. support logic ................................................... ................................................... ........... - 39 - 8.1 clock control & reset 32k ................................................... ............................................ - 40 - 8.1.1 overview ................................................... ................................................... ............... - 40 - 8.1.2 functionality ................................................... ................................................... ......... - 40 - 8.1.3 clock enable register ................................................... ............................................... - 40 - 8.2 interrupt control ................................................... ................................................... ........ - 41 - 8.2.1 overview ................................................... ................................................... ............... - 41 - 8.2.2 functionality ................................................... ................................................... ......... - 41 - 8.2.3 interrupt registers ................................................... ................................................... . - 43 - 8.2.4 extends of interrupt ................................................... .................................................. - 44 - 8.3 ringer tone generator ................................................... .................................................. - 45 - 8.3.1 overview ................................................... ................................................... ............... - 45 - 8.3.2 functionality ................................................... ................................................... ......... - 45 - 8.3.3 sounder tone register definition ................................................... ............................. - 46 - 8.3.4 sounder volume register definition ................................................... ........................ - 46 - 8.3.5 example of use ................................................... ................................................... ...... - 46 - 8.3.6 sounder registers ................................................... ................................................... .. - 47 - 8.4 piezo tone generator ................................................... .................................................. - 48 - 8.4.1 overview ................................................... ................................................... ............... - 48 - 8.4.2 functionality ................................................... ................................................... ......... - 48 - 9. interface logic ................................................... ................................................... ....... - 49 - 9.1 keypad scanner ................................................... ................................................... ......... - 49 - 9.1.1 overview ................................................... ................................................... ............... - 49 - 9.1.2 use of the keypad scanner ................................................... ....................................... - 50 - 9.1.3 use of a software keypad scanner ................................................... ............................ - 50 - 9.2 i/o ports ................................................... ................................................... .................... - 50 - 9.3 keypad control registers ................................................... ............................................. - 51 - 9.3.1 key location and size programming ................................................... ........................ - 53 - 9.4 timers ................................................... ................................................... ........................ - 53 - 9.4.1 watch dog control ................................................... ................................................... - 54 - 9.4.2 timer 1ms control1 ................................................... .................................................. - 54 - 9.4.3 timer control ................................................... ................................................... ........ - 54 - 9.4.4 1s counter ................................................... ................................................... ............. - 55 - 9.4.5 watch dog kick ................................................... ................................................... ..... - 55 - 9.4.6 1ms counter ................................................... ................................................... .......... - 55 - 10. speech interface ................................................... ................................................... ..... - 56 - 10.1 overview ................................................... ................................................... ................... - 56 - 10.2 functionality ................................................... ................................................... .............. - 56 - 10.3 pcm serial interface ................................................... ................................................... ... - 57 - 10.3.1 use with additional external lines ................................................... .......................... - 57 - 10.3.2 i/o ports ................................................... ................................................... ............... - 57 - 10.3.3 status of speech interface when reset ................................................... ...................... - 58 - 10.4 internal codec control ................................................... ............................................... - 58 - 10.5 pcm interface registers ................................................... ................................................ - 5 8 - 10.5.1 speech control 0 ................................................... ................................................... .... - 58 - W681307 publication release date: may, 2007 revision 1.3 - 5 - 10.5.2 specific register ................................................... ................................................... ..... - 58 - 10.5.3 speech io direction ................................................... .................................................. - 59 - 10.5.4 speech io input data ................................................... ................................................ - 5 9 - 10.5.5 speech io output data ................................................... ............................................. - 59 - 10.5.6 speech io mask ................................................... ................................................... ..... - 60 - 10.5.7 fsync counter ................................................... ................................................... ....... - 60 - 10.6 the multiplexer to connect 5 pcm channels to 4 proc essor channels ................................ - 60 - 10.6.1 multiplexer control register ................................................... ...................................... - 60 - 10.7 pcm highway interface ................................................... ................................................ - 6 1 - 10.7.1 the introduction of pcm modes ................................................... .............................. - 61 - 10.7.2 the description of pcm highway interface registers ................................................. - 63 - 10.8 digital gain multiplexer ................................................... ............................................... - 66 - 10.8.1 fine-tuning gain stage registers ................................................... ............................. - 66 - 11. processor interface ................................................... ................................................. - 70 - 11.1 overview ................................................... ................................................... ................... - 70 - 11.2 functionality ................................................... ................................................... .............. - 70 - 11.3 processor access sequencer ................................................... .......................................... - 70 - 11.4 read multiplexer ................................................... ................................................... ....... - 73 - 11.5 processor interface control registers ................................................... ............................ - 73 - 11.5.1 auxopport ................................................... ................................................... ............ - 73 - 11.5.2 diagsel ................................................... ................................................... .................. - 74 - 11.5.3 diag_cs ................................................... ................................................... ................. - 75 - 11.5.4 diag_cs3 ................................................... ................................................... ............... - 76 - 11.5.5 multiplier_enable ................................................... ................................................... .. - 77 - 11.6 in system programming mode ................................................... ...................................... - 77 - 11.6.1 hardware setting usage ................................................... ........................................... - 77 - 11.6.2 software command usage ................................................... ....................................... - 77 - 11.6.3 isp_ctrl (hardware & watchdog reset control registe r) ......................................... - 78 - 11.6.4 specific register ................................................... ................................................... ..... - 78 - 11.7 mask rom mode ................................................... ................................................... ..... - 79 - 11.7.1 usage ................................................... ................................................... ..................... - 79 - 12. speech processor ................................................... ................................................... .... - 80 - 12.1 transcoder dsp ................................................... ................................................... .......... - 80 - 12.2 the description of the activation registers ................................................... ................... - 81 - 12.2.1 mixer_en ................................................... ................................................... ............ - 81 - 12.2.2 speech logic_en ................................................... ................................................ - 8 1 - 12.3 the description of transcoder dsp registers ................................................... ................ - 81 - 12.3.1 connect0 ................................................... ................................................... ................ - 82 - 12.3.2 specified register ................................................... ................................................... .. - 82 - 12.3.3 specified register ................................................... ................................................... .. - 82 - 12.3.4 specified register ................................................... ................................................... .. - 82 - 12.3.5 pcmmode0 ................................................... ................................................... ............ - 83 - 12.3.6 inputgain0 ................................................... ................................................... ............ - 83 - 12.3.7 outputgain0 ................................................... ................................................... ......... - 83 - 12.3.8 tonefreqa0 ................................................... ................................................... ........... - 83 - 12.3.9 tonefreqb0 ................................................... ................................................... ........... - 84 - 12.3.10 tonevola0 ................................................... ................................................... ............ - 84 - 12.3.11 tonevolb0 ................................................... ................................................... ............. - 84 - W681307 publication release date: may, 2007 revision 1.3 - 6 - 12.3.12 toneena0 ................................................... ................................................... ............... - 84 - 12.3.13 sidetone ................................................... ................................................... ................ - 85 - 12.3.14 loopback_en ................................................... ................................................... ........ - 85 - 12.3.15 specified register ................................................... ................................................... .. - 85 - 12.3.16 connect1 ~ toneena1 ................................................... ............................................... - 85 - 12.3.17 connect2 ~ toneena2 ................................................... ............................................... - 85 - 12.3.18 sidetonechannel_ena ................................................... .............................................. - 86 - 12.3.19 connect3 ~ toneena3 ................................................... ............................................... - 86 - 12.4 pcm mixer matrix ................................................... ................................................... ..... - 86 - 12.5 gain tables ................................................... ................................................... ................ - 86 - 13. echo canceller ................................................... ................................................... ...... - 89 - 13.1 half aec block diagram ................................................... .............................................. - 89 - 13.1.1 acoustics suppression ................................................... .............................................. - 89 - 13.1.2 network power estimation ................................................... ....................................... - 90 - 13.1.3 acoustic power estimation ................................................... ....................................... - 90 - 13.1.4 auto gain control ................................................... ................................................... . - 91 - 13.2 the software interface of speech processor ................................................... ................... - 91 - 13.3 activation registers ................................................... ................................................... ... - 91 - 13.3.1 up_config ................................................... ................................................... .......... - 91 - 13.3.2 up_reset ................................................... ................................................... ............. - 92 - 13.3.3 ec_belta ................................................... ................................................... ............ - 92 - 13.3.4 specific register ................................................... ................................................... ..... - 92 - 13.4 performance adjustment registers ................................................... ............................... - 92 - 13.4.1 acoustic suppressor register ................................................... ................................... - 92 - 13.4.2 acoustic side control registers ................................................... ................................ - 93 - 13.4.3 network side control registers ................................................... ................................ - 95 - 13.4.4 acoustic / network active status ................................................... ................... - 98 - 13.4.5 agc control registers ................................................... ............................................. - 98 - 13.4.6 noise suppressor registers ................................................... ..................................... - 100 - 13.4.7 aec soft clip ................................................... ................................................... ...... - 101 - 13.5 acoustic side / network side power measurement ................................................... .... - 106 - 13.5.1 acoustic_short_term_power ................................................... .................... - 106 - 13.5.2 acoustic_long_term_power ................................................... ...................... - 106 - 13.5.3 acoustic_power_deviation ................................................... ........................ - 107 - 13.5.4 acoustic / network active status ................................................... ................. - 107 - 13.5.5 network_short_term_power ................................................... .................... - 107 - 13.5.6 network_long_term_power ................................................... ...................... - 108 - 13.5.7 network_power_deviation ................................................... ........................ - 108 - 13.5.8 acoustic / network active status ................................................... ................. - 108 - 14. system function ................................................... ................................................... .... - 109 - 14.1 power on reset ................................................... ................................................... ........ - 109 - 14.1.1 codec on/off scheme ................................................... ......................................... - 109 - 14.1.2 codec digital part ................................................... ................................................ - 1 10 - W681307 publication release date: may, 2007 revision 1.3 - 7 - 14.2 adc adaptive bit flip probability ................................................... .............................. - 110 - 14.3 sounder signal selection ................................................... ............................................. - 111 - 14.4 frequency adjustment of crystal oscillator ................................................... ................ - 112 - 14.5 specific register ................................................... ................................................... ....... - 113 - 14.6 vag selection ................................................... ................................................... .......... - 113 - 14.7 tg gain register ................................................... ................................................... ...... - 114 - 14.8 po gain register ................................................... ................................................... ...... - 115 - 14.9 the pcm codec ................................................... ................................................... .... - 117 - 14.9.1 block diagram ................................................... ................................................... ..... - 117 - 14.9.2 analog interface and signal path ................................................... ............................ - 117 - 14.9.3 control register: codec_ctrl ................................................... ............................ - 118 - 14.9.4 specific register ................................................... ................................................... ... - 119 - 14.9.5 specific register ................................................... ................................................... ... - 119 - 14.10 receive_diag ................................................... ................................................... ....... - 119 - 14.11 specific register ................................................... ................................................... ....... - 121 - 14.12 enallclock ................................................... ................................................... ............... - 121 - 14.13 codec_test_sel ................................................... ................................................... ..... - 121 - 14.14 test_sysclkout ................................................... ................................................... .... - 122 - 14.15 bgp_lpf_en ................................................... ................................................... ........... - 122 - 14.16 codec status indicator ................................................... .............................................. - 122 - 14.17 bandgap voltage adjustment ................................................... ..................................... - 123 - 14.18 specific register ................................................... ................................................... ....... - 123 - 14.19 linear regulator voltage controller register ................................................... .............. - 123 - 14.20 core pwr_det ................................................... ................................................... ......... - 124 - 14.21 da high pass filter selection ................................................... ...................................... - 124 - 14.22 ti path selection ................................................... ................................................... ....... - 125 - 15. serial peripheral interface ................................................... ................................ - 127 - 15.1 serial peripheral interface ? spi signals ................................................... ....................... - 127 - 15.1.1 spi_control 0 ................................................... ................................................... ....... - 128 - 15.1.2 spi_control 1 ................................................... ................................................... ....... - 128 - 15.1.3 spi status ................................................... ................................................... ............. - 129 - 15.1.4 spi interrupt enable ................................................... ............................................... - 12 9 - 15.1.5 dumpbyte ................................................... ................................................... ........... - 129 - 15.1.6 write tx fifo ................................................... ................................................... ..... - 129 - 15.1.7 read rx fifo ................................................... ................................................... ...... - 130 - 15.1.8 spi_transfer_size ................................................... ................................................... - 130 - 15.1.9 spi_start_rtx ................................................... ................................................... ........ - 130 - 16. spi for serial data flash ................................................... ...................................... - 131 - 16.1 introduction to spi of serial data flash ................................................... ....................... - 131 - 16.2 block diagram ................................................... ................................................... ......... - 131 - 16.3 data format ................................................... ................................................... ............. - 132 - 16.4 fsm ................................................... ................................................... .......................... - 134 - 16.5 fifo/ram ................................................... ................................................... .............. - 134 - 16.6 interrupt ................................................... ................................................... .................. - 134 - 16.7 df_spi register group ................................................... ............................................... - 13 4 - 16.7.1 df_clk ................................................... ................................................... ............... - 134 - 16.7.2 df_cmd_len ................................................... ................................................... .... - 135 - 16.7.3 df_data_len ................................................... ................................................... .. - 135 - W681307 publication release date: may, 2007 revision 1.3 - 8 - 16.7.4 df_intr_reg ................................................... ................................................... .... - 135 - 16.7.5 df_cmd_b1 ~ df_cmd b5 ................................................... ................................... - 136 - 16.7.6 df_clk_format ................................................... ................................................ - 1 37 - 16.7.7 df_fifo_data ................................................... ................................................... .. - 138 - 16.7.8 df_cnt ................................................... ................................................... .............. - 138 - 16.7.9 df_wr_cnt ................................................... ................................................... ....... - 139 - 16.7.10 df_rd_cnt ................................................... ................................................... ....... - 139 - 16.8 example of w25x20/40/80 serial flash ................................................... ...................... - 139 - 17. winbond 2-wire serial bus ................................................... .................................... - 141 - 17.1 introduction to winbond 2-wire serial bus ................................................... ................. - 141 - 17.2 the description of w2s register ................................................... ................................. - 141 - 17.2.1 w2s_enable ................................................... ................................................... ......... - 141 - 17.2.2 eeprom_config ................................................... ................................................... . - 142 - 17.2.3 prescale_lo ................................................... ................................................... .......... - 142 - 17.2.4 prescale_hi ................................................... ................................................... .......... - 142 - 17.2.5 rdwrfifo ................................................... ................................................... ........... - 143 - 17.2.6 force_activity ................................................... ................................................... ..... - 143 - 17.2.7 w2s_status ................................................... ................................................... .......... - 143 - 17.2.8 fifordptr ................................................... ................................................... ........... - 144 - 17.2.9 fifowrptr ................................................... ................................................... ........... - 144 - 17.2.10 forceackfail ................................................... ................................................... ........ - 144 - 17.2.11 w2s_misc ................................................... ................................................... ............ - 144 - 18. usb device controller and transceiver ................................................... ....... - 145 - 18.1 overview ................................................... ................................................... ................. - 145 - 18.2 functionality ................................................... ................................................... ............ - 145 - 18.2.1 endpoints ................................................... ................................................... ............ - 146 - 18.2.2 descriptor rom ................................................... ................................................... ... - 146 - 18.2.3 configurations and interfaces ................................................... ................................. - 147 - 18.2.4 audio class ................................................... ................................................... ......... - 148 - 18.2.5 hid class ................................................... ................................................... ............ - 149 - 18.2.6 usb isp mode ................................................... ................................................... ...... - 150 - 18.2.7 vendor command ................................................... .................................................. - 150 - 18.3 usb registers ................................................... ................................................... ........... - 150 - 18.3.1 usb enable register ................................................... ............................................... - 15 0 - 18.3.2 usb interrupt register a ................................................... ........................................ - 150 - 18.3.3 usb interrupt register b ................................................... ......................................... - 151 - 18.3.4 endpoint 0 ? control in/out registers ................................................... ................... - 152 - 18.3.5 endpoint 1 and 2 ? iso in/out registers ................................................... ................ - 153 - 18.3.6 endpoint 3 ? bulk in registers ................................................... ................................ - 155 - 18.3.7 endpoint 4 ? bulk out registers ................................................... ............................. - 156 - 18.3.8 endpoint 5 ? interrupt in registers ................................................... ......................... - 157 - 18.3.9 specific register ................................................... ................................................... ... - 158 - 18.3.10 specific register ................................................... ................................................... ... - 158 - 18.3.11 specific register ................................................... ................................................... ... - 158 - 19. package dimensions ................................................... ............................................... - 15 9 - W681307 publication release date: may, 2007 revision 1.3 - 9 - 1. general description the main product targets for the usb codec mcu chip are ? 27.648mhz four cycle 8032 mcu ? support external flash and easy transfer to low cos t mask rom production ? universal serial bus (usb) v1.1 compliant device co ntroller and phy, capable of full speed communicati on (12mhz) with up to 5 configuration end ?points ? 8khz voice sampling rate and 16bits of adc/dac ? support aec/agc for on-chip speaker phone support ? support keypad function winbond mcu chip will be available in the following package device package description W681307d xxxx 100 pin lqfp normal mode, mask rom 32 k, x2 clk W681307 publication release date: may, 2007 revision 1.3 - 10 - 2. features micro controller ? embedded 27.648mhz winbond ? turbo 8032 micro-controller with 4 clocks per mach ine cycle ? 4k system ram, 32k mask rom ? core 1.9v, i/o 3.3v ? power on reset circuit ? software power down mode ? in system programming (isp) for 29/39/49 series fla sh rom ? built-in keypad scan, watchdog, wait state speech processor/interface ? 4 processor channels ? programmable input/output gain stage ? programmable auto gain control (agc) stage ? programmable soft clip gain stage ? acoustic echo cancellation (aec) with half duplex, absolute/relative mode ? pcm interface for external codec or pcm interface ? sndr output ? built in dtmf tone generator pcm codec ? one built-in pcm codec ? analogue input amplifier with internal programmable gain stage ? analog output amplifier: push pull drive, internal programmable gain stage usb 1.1 ? universal serial bus usb v1.1 compliant device cont roller and phy, capable of full speed communication (12mhz) with up to 5 configuration end ?points. uart ? t8032 uart for data transmit application. pcm highway ? the 1 st pcm highway has four channels.. ? all channels support 8/16 bits pcm format, and iom2 mode. ? works in master or slave modes with external codec. w2s ? support three eeprom format page modes. ? support six kinds of w2s bus clocks. spi interface ? works in master or slave modes. spi flash interface ? works in master with the winbond spi interface of s eries flash. isp ? in-system-programming capability with software comm and via uart or usb interface. package ? 100 pin lqfp package W681307 publication release date: may, 2007 revision 1.3 - 11 - 3. pin configuration resetc reg_ctrl vag vgap agnd1 avdd1 9594 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 100 9998 97 96 po2n ti 1 t i 1 t i 2 t i 2 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 9 8 7 6 5 4 3 2 1 31 32 33 34 35 36 37 38 42 43 44 45 46 47 48 49 50 26 27 28 29 30 75 74 73 72 71 70 59 58 57 56 55 54 53 52 51 69 68 67 66 65 64 63 62 61 60 39 40 41 ad0 ad1 ad2 ale dvdd4 ad7 ad6 ad5 ad4 ad3 isp_wr psen pcm_in pcm_ out pcm_ clk pcm_fsc kc1 kc2 kc3 kc0 kr1 kr2 kr4 kr3 sndr_ref_clk nc vss_reg vdd_reg dvdd1 dgnd1 nc a14 a13 a12 a11 a10 a9 a8 p1.0 wr p1.1 p1.2/sda p1.5/mosi/sd i p1.6/miso/sdo p1.4/sck p1.3/scl dgnd2 dvdd2 p3.1(txd0) p3.0(rxd0) rd p3.5 /a1 / cs3 p3.4 /a0 cs2 / spi_cs cs1/ df_cs nc sysclkout nc nc ext_rom nc dgnd5 xtal1 dvdd5 reset_ out xtal2 dvdd3 dgnd3 vdd_ osc nc gnd_ osc kr0 pll_lpf usb_dp usb_dn vss_usb vdd_usb lqfp 100 pin mask rom nc nc nc nc nc W681307 d (isp_en) avdd2 po1n po1p po2 p agnd 2 nc nc W681307 publication release date: may, 2007 revision 1.3 - 12 - 4. pins description pin no. pin name i/o state during reset state after reset pin type section function description alternative function 1 kr0 i/o input h input h pc3b01u keypad scan row output gpio 2 kr1 i/o input h input h pc3b01u keypad scan row output gpio 3 kr2 i/o input h input h pc3b01u keypad scan row output gpio 4 kr3 i/o input h input h pc3b01u keypad scan row output gpio 5 kr4 i/o input h input h pc3b01u keypad scan row output gpio 6 kc0 i/o input l input l pc3b01d keypad scan column input gpio 7 kc1 i/o input l input l pc3b01d keypad scan column input gpio 8 kc2 i/o input l input l pc3b01d keypad scan column input gpio 9 kc3 i/o input l input l pc3b01d keypad scan column input gpio 10 pcm_in i/o input h input h pc3b02u pcm high way, data input gpio 11 pcm_out i/o input h input h pc3b02u pcm high way, data output gpio 12 pcm_clk i/o input l input l pc3b02d pcm high way, clock in/output gpio 13 pcm_fsc i/o input l input l pc3b02d pcm high way, frame pluse in/output gpio 14 isp_ wr o input h input h pc3b02u in the normal mode operation, this pin is high. in the in- system-programming (prog) state, this pin is used f or wr function for writing flash memory program. 15 psen o input h output h pc3b02u 8032t for program memory strobe enable 16 ale i/o input h output h pc3b02u output address latch enable (ale) function 17 dvdd4 pwr - - pvddc digital supply voltage 4 (for digital i/o pads power) 18 ad7 i/o input h input h pc3b02u 8032t multiplexed address/data pin 7 19 ad6 i/o input h input h pc3b02u 8032t multiplexed address/data pin 6 20 ad5 i/o input h input h pc3b02u 8032t multiplexed address/data pin 5 21 ad4 i/o input h input h pc3b02u 8032t multiplexed address/data pin 4 22 ad3 i/o input h input h pc3b02u 8032t multiplexed address/data pin 3 23 ad2 i/o input h input h pc3b02u 8032t multiplexed address/data pin 2 24 ad1 i/o input h input h pc3b02u 8032t multiplexed address/data pin 1 25 ad0 i/o input h input h pc3b02u 8032t multiplexed address/data pin 0 26 dvdd2 pwr - - pvddr digital supply voltage 2 (for digital i/o pads power) 27 dgnd2 pwr - - pvssr digital ground 2 (i/o ground) W681307 publication release date: may, 2007 revision 1.3 - 13 - 29 a9 i/o input h output h pc3b02u 8032t address line 9 30 a10 i/o input h output h pc3b02u 8032t address line 10 31 a11 i/o input h output h pc3b02u 8032t address line 11 32 a12 i/o input h output h pc3b02u 8032t address line 12 33 a13 i/o input h output h pc3b02u 8032t address line 13 34 a14 i/o input h output h pc3b02u 8032t address line 14 35 nc i/o input h output h pc3b02u no connection 36 p3.5 /a1 i/o input h input h pc3b02u port3 bit 5 of 8032t 37 p3.4 /a0 i/o input h input h pc3b02u port3 bit 4 of 8032t 38 p3.1 /txd0 i/o input h input h pc3b02u port 3 bit 1 or txd serial transmit data port of in ternal 8032 turbo 39 p3.0 /rxd0 i/o input h input h pc3b02u port 3 bit 0 or rxd serial receive data port of int ernal 8032 turbo 40 cs2 / cs spi _ i/o input h output h pc3t02 external chip select general purpose output 41 cs1 / cs df _ i/o input h output h pc3t02 external chip select general purpose output 42 r d /p3.7 i/o input h input h pc3b02u 8032t read strobe p3.7 is 8032 i/o 43 wr / p3.6 i/o input h input h pc3b02u 8032t write strobe p3.6 is 8032 i/o 44 p1.6 /miso/sdi i/o input h input h pc3b02u port 1 bit 6 spi function 45 p1.5 /mosi/sdo / 3 cs i/o input h input h pc3b02u port 1 bit 5 spi function or external chip select 46 p1.4 /sck i/o input h input h pc3b02u port 1 bit 4 or spi interface clock output this pin also supports wait state function. 47 p1.3 /scl i/o input h input h pc3b02u port 1 bit 3 or w2s interface clock output of progr amming eeprom. 48 p1.2 /sda i/o input h input h pc3b02u port 1 bit 2 or w2s interface serial data of progra mming eeprom. 49 p1.1 i/o input h input h pc3b02u port 1 bit 1 50 p1.0 i/o input h input h pc3b02u port 1 bit 0 51 ext_rom i input h input pc3d01u when set this pin to high then the chip goes into e xternal rom mode. 52 dgnd3 pwr - - pvssc digital ground 3 (core power ground) 53 dvdd3 pwr - - pvddc digital supply voltage 3 for core power, which shou ld connect to dvdd1. 54 vdd_osc pwr - - pvddc oscillation circuits supply voltage. 55 xtal1 i active active panalog 13.824mhz crystal oscillator output 56 xtal2 o active active panalog 13.824mhz crystal oscillator input 57 gnd_osc pwr - - pvssc oscillation circuits ground W681307 publication release date: may, 2007 revision 1.3 - 14 - 58 resetout o l h pc3o01 chip reset indication output. active high after the reset state. 59 dvdd5 pwr - - pvddc digital supply voltage 5 (for digital i/o pads power) 60 dgnd5 pwr - - pvssc digital ground 5 (i/o ground) 61 nc o tristate tristate pc3t02 no connection 62 sysclkout o tristate l pc3t02 13.824 mhz system clock output 63 nc o tristate tristate pc3t02 no connection 64 nc o tristate tristate pc3t01 no connection 65 nc o tristate tristate pc3b01 no connection 66 nc o tristate tristate pc3t01 no connection 67 nc o tristate tristate pc3t01 no connection 68 nc o tristate tristate pc3t02 no connection 69 nc o tristate tristate pc3t02 no connection 70 nc o tristate tristate pc3t02 no connection 71 nc o tristate tristate pc3t01 no connection 72 nc o tristate tristate analog no connection 73 nc i hi-z hi-z analog no connection 74 agnd2 pwr - - pvssc analog ground for op2 output amplifier 75 po1p o tristate tristate panalog power amplifier output (non-inverting) - this pin i s the non- inverting power amplifier output, which is an inver ted version of the signal at po1n. this pin is capable of driving a 120 load to po1n at 3v supply power. this pin is d.c. referred to the vag pin. this pin is tri- state when the chip is in analog codec power down mode. 76 po1n o tristate tristate panalog power amplifier output (inverting) - this pin is the inverting power amplifier output. this pin is capable of driv in g a 120 load to po1p at 3v supply voltage. this pin is d.c . referenced to the vag pin. the po1p and po1n output s are differential. this pin is tri- state when the chip is in analog codec power down mode. 77 po2p o tristate tristate panalog power amplifier output (non-inverting) - this pin i s the non- inverting power amplifier output, which is an inver ted version of the signal at po2n. this pin is capable of driving a 16 load to po2n at 3v supply power. this pin is d.c. referred to the vag pin. this pin is tri- state when the chip is in analog codec power down mode. 78 po2n o tristate tristate panalog power amplifier output (inverting) - this pin is the inverting power amplifier output. this pin is capable of driv ing a 16 load to po2p at 3v supply voltag e. this pin is d.c. referenced to the vag pin. the po2p and po2n output s are differential. this pin is tri- state when the chip is in analog codec power down mode. 79 avdd2 pwr - - pvddc analog supply voltage for op2 amplifier 80 avdd1 pwr - - pvddc analog supply voltage 81 resetc o tristate tristate panalog it should connect a capacitor for internal power on reset circuit. 82 reg_ctrl o active active panalog output signal of 3v linear regulator to drive the p np transistor. 83 vag o tristate 1.5v panalog analog reference voltage. this pin possesses the an alog virtual ground of internal codec circuits. 84 vbgp o 1. 0v 1.0v panalog the band gap output voltage. it is 1.0 v volt typically. 85 agnd1 pwr - - pvssc analog ground 86 ti1+ i hi-z hi-z panalog this is the non-inverting input of the transmission operational amplifier tg1. 87 ti1- i hi-z hi-z panalog this is the inverting input of the transmission ope rational amplifier tg1. 88 ti2+ i hi-z hi-z panalog this is the non-inverting input of the tr ansmission operational amplifier tg2. 89 ti2- i hi-z hi-z panalog this is the non- inverting input of the transmission operational amplifier tg2. W681307 publication release date: may, 2007 revision 1.3 - 15 - p1.3 0 w2 s_ena 0x1740[7] & ~(w2s_prot_sel 0x1740 [6]) 0 p1. 2 1 p1.2 1 01 scl p1.3 sda sda w2s_ena 0x1740[7 ]& ~(w2s_prot_sel 0x1740 [6]) w2s_ena 0x1740[7 ]& (w2 s_ prot_sel 0x1740[6 ]) 0 1 01 scl p1.4 df_sck w2 s_ena 0x1740[7] & (w2s_ prot_sel 0x1740[6 ]) df _enb 0x1730[7] 0 1 spi_sck spi_enb 0x1720 [7] 0 1 piezo_enb 0x144 b[ 0] p1. 4 piezo_clk 90 vss_reg pwr - - pvssc ground of 3.0v linear regulator. 91 vdd_reg pwr - - pvddc 3.3v input of 3.0v linear regulator. 92 dvdd1 pwr - - pvddc 1.9v linear regulator output for internal digital core power supply. connect a large capacitor (>10uf) for output regulation. 93 dgnd1 pwr - - pvssc digital ground 1 (core power ground) 94 pll_lpf o tristate tristate panalog internal 48mhz pll charge pump output. put a passiv e lpf filter in the pin to ground. 95 vss_usb pwr - - pvssc usb analog front end ground. 96 usb_dp analog i/o hi-z hi-z panalog usb d+ connection. series termination resis tors (22 & 1%) are required for impedance of usb bus. the usb spec 1.1 states that the impedance of each driver is require d to be between 28 and 44 & . this chip drive output resistance is 8 to 10 & . therefore, the 22 & 1% series resistors are used. 97 usb_dn a nalog i/o hi-z hi-z panalog usb d- connection. series termination resistors (22 & 1%) are required for impedance of usb bus. the usb spec 1.1 states that the impedance of each driver is require d to be between 28 and 44 & . this chip drive output resistance is 8 to 10 & . therefore, the 22 & 1% series resistors are used. 98 vdd_usb pwr - - pvddc usb analog front end supply power. full speed devices a re identified by pulling d+ to 3.3v0.3 volts via a 1. 5k & 5 % resistor. the baseband chip inside has been built i n t he 1.5k & 20% resistor and the default is disconnected to vdd_usb. the 99 nc i input input pc3d21 no connection 100 sndr o output l output l pc3b02u sounder output - this is a control pin to turn on/off the external transistor, which is used to supply th e high peak currents that magnetic sounders typically require. * when /cs2 is pull low in the initial power on sta te. then the chip will enter into the hardware isp mode to download the system program code via uart or usb po rts. * p1.2; p1.3 and p1.4 multiple functions W681307 publication release date: may, 2007 revision 1.3 - 16 - p3.4 01 a0 p3.4_a0_sel 150c[5] sim_clk uart_en & sim_en 1554[7-6] p3.4/ a0/ rxd1/sim_clk p3.5 01 a1 p3.5_a1_sel 150c[6] 01 uart_txd1 uart_en 1554[7] p3.5/ a1/ txd1 00 10 01 11 uart_rxd1 x p1.6_ sel [1:0] ( 0x150c [1: 0 ] ) 2 10 p1.5 p1.6 p1.5_ sel [b2] ( 0x150c [b2] ) 10 0 spi_ enb 0 spi_ enb mosi ( spi master output ; slave input) 1 sdi (df_spi) p 1.5/ mosi / sdi 1 01 sdo (df_spi) df_ enb p1.6/miso / sdo miso ( spi master input ; slave output ) x x x cs3_enable [b4] ( 0x150c [b4] ) 10 /cs3 3 p1.6 /cs3 / * p1.5 and p1.6 multiple functions * p3.4 and p3.5 multiple functions W681307 publication release date: may, 2007 revision 1.3 - 17 - 5. system diagram 5.1 function block diagram the function block diagrams of the mcu chip and spe ech interface are shown below 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 100 99 98 97 96 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 9 8 7 6 5 4 3 2 1 31 32 33 34 35 36 37 38 42 43 44 45 46 47 48 49 50 26 27 28 29 30 75 74 73 72 71 70 59 58 57 56 55 54 53 52 51 69 68 67 66 65 64 63 62 61 60 39 40 41 winbond turbo 8032 32k mask rom codec aec pcm & mixer 4k ram keypad w2s spi uart usb W681307 publication release date: may, 2007 revision 1.3 - 18 - 5.2 i/o cells in winbond mcu chip chartered semiconductor (artisan) 0.25um integral i /o cell library pc3b02u 3v cmos 3-state i/o pad with pull-up resistor, 2ma vdd pad i oen cin figure 5-1: pc3b02u pad pc3b02d 3v cmos 3-state i/o pad with pull-down resistor, 2m a pad i oen cin vss figure 5-2: pc3b02d pad pc3o02 3v cmos output pad, 2ma i pad figure 5-3: pc3o02 pad pc3d01d 3v cmos input only pad with pull-down resistor vss pad cin figure 5-4: pc3d01d pad W681307 publication release date: may, 2007 revision 1.3 - 19 - pc3d01u 3v cmos input only pad with pull-up resistor vdd pad cin figure 5-5: pc3d01u pad pc3d21u 3v cmos schmitt non inverting input only pad with p ull-up resistor vdd pad cin figure 5-6: pc3d01d pad pc3t01/02 3v cmos 3-state output pad, 1ma/2ma pad i oen figure 5-7: pc3t01 pad W681307 publication release date: may, 2007 revision 1.3 - 20 - 6. electrical characteristics 6.1 absolute maximum ratings (voltage referenced to agnd pin) parameter symbol rating unit core power supply voltage, pin 53, 92 dvdd 1.9 v i/o power supply voltage, pin 17, 26, 59 iovdd 2.7 ~ 3.6 v power supply voltage , pin 80 avdd 3.0 ~ 3.6 v dc supply voltage for usb ouput stage vdd_usb 3.0 ~ 3.6 v operating temperature top -10 to +55 storage temperature tstg -85 to +85 note: exposure to conditions beyond those listed un der absolute maximum ratings may adversely affect t he life and reliability of the device. 6.2 dc characteristics (agnd = 0 volt t op = -10 to +55 ) parameter sym. condition min. typ. max . unit core operating current i core - 6 - ma i/o operating current i i/o - 6 - ma analog operating current i ana 5 ma input high voltage v ih all digital input pins vdd 0.7 - - v input low voltage v il all digital input pins 0 - vdd 0.3 v output high voltage v oh dt, ssp tx vdd 0.75 - - v output low voltage v ol dt, ssp tx 0 - vdd 0.25 v input high current i il agnd vin avdd -10 - +10 a input low current iih agnd vin avdd -10 - +10 a input capacitance cin all digital input pins to agnd - - 10 pf W681307 publication release date: may, 2007 revision 1.3 - 21 - 6.3 analog transmission characteristics (avdd =+3.0v 5%, agnd = 0 volt , top = -10 to +55 c ; all analog signal referenced to vag; 64 kbps p cm; fst = fsr = 8 khz; bclkt = bclkr = 1.536 mhz; mclk = 13.824 mhz ; unless other wise noted) 6.3.1 amplitude response for analog transmission performa nce a/d d/a parameter sym. condition typ. min. max. min. max. unit absolute level * l abs 0 dbm0 = -3.0 dbm @ 600 ? 0.549 --- --- --- --- vrms max. transmit level t xmax --- vag - 1db --- --- --- --- vpk 15 hz --- --- --- -60 -0.5 50 hz --- --- --- -40 -0.5 100 hz --- --- --- -20 -0.5 200 hz --- --- -3 -5 -0.5 300 to 3000 hz --- --- -0.20 +0.15 -0.20 3300 hz --- --- -0.35 +0.15 -0.35 3400 hz --- --- -0.5 0 -0.5 4000 hz --- --- --- -12 --- frequency response, relative to 0 dbm0 @ 1020hz g rtv 4600 to 7000 hz --- --- --- -40 --- db +3 to -40 dbm0 --- -0.3 +0.3 -0.2 +0.2 -40 to -50 dbm0 --- -1.0 +1.0 -0.4 +0.4 gain variation vs level tone (1020 hz relative to -10 dbm0) g lt -50 to -55 dbm0 --- -1.6 +1.6 -0.8 +0.8 db 6.3.2 distortion characteristics for analog transmission performance transmit receive parameter sym. condition typ . min. ma x. mi n. ma x. unit absolute group delay d abs 1600 hz --- --- 250 --- 200 s group delay referenced to 1600 hz d rtv 500 to 600 hz 600 to 1000 hz 1000 to 2600 hz 2600 to 2800 hz 2800 to 3000 hz --- --- --- --- --- --- --- --- --- --- 250 200 70 100 145 --- --- --- --- --- 30 20 70 120 200 s total distortion vs. level tone (1020 hz, mu-law, c- message) d lt +3 dbm0 0 to -30 dbm0 -40 dbm0 -45 dbm0 --- --- --- --- 36 36 29 25 --- --- --- --- 34 36 30 25 --- --- --- --- dbc W681307 publication release date: may, 2007 revision 1.3 - 22 - 6.4 analog electrical characteristics (op amplifer tg and vag; av dd = +3.0v 5%, agnd = 0v; top = -10 to +55 c) parameter sym. conditions min. typ. max. unit input current of tg ti1+, ti1- ti2+, ti2- --- 0.01 1.0 a ac input impedance to vag for tg (1 khz) r tiin ti1+, ti1- ti2+, ti2- --- 1.0 m input capacitance of tg c tiin ti1+, ti1- ti2+, ti2- --- --- pf input offset voltage of tg v ofin ti1+, ti1- ti2+, ti2- --- --- 25 ? mv input common mode voltage of tg v cmv ti1+, ti1- ti2+, ti2- 0.5 --- avdd? 0.8 v input common mode rejection ratio of tg ti1+, ti1- ti2+, ti2- 60 100 db gain bandwidth product of tg (10khz) r load 10 k ? ti1+, ti1- ti2+, ti2- 975 khz dc open loop gain of tg r load 10 k ? ti1+, ti1- ti2+, ti2- 80 95 db bandgap voltage v bgap ref to agnd 1.0 v vag output voltage v vag ref to agnd 1.5 v vag output current with less than 50 mv change in output voltage i vag v vag 3 50mv ? 1 ? ma power supply rejection ratio psrr tg --- 55 --- db 6.5 power drivers ? po1, 2 ( av dd = +3.0v 5%, agnd = 0v; top = -10 to +55 c) parameter sym. conditions min. typ. max. unit output offset voltage of po1+ (po2+) relative to po1- (po2-) inverted unity gain for po- 30 mv po1+ (po2+) , po1- (po2-) output current @ vag=1.5v, r l =120, thd<1% vag-0.7 v po+ ,po- vag+0.7 v 6 ma po1+ (po2+) , po1- (po2-) output resistance inverted unity gain for po- 10 & gain bandwidth product @ 10 khz open loop for po- 433 khz load capacitance for po c lap po- to po+ --- --- 300 pf gain of po1+ (po2+) relative to po1- (po2-) 0 0.2 db load resistance differentially for po1 r ldap po1- to po1+ --- 120 --- & load resistance differentially for po2 r ldap po2- to po2+ --- 16 --- & W681307 publication release date: may, 2007 revision 1.3 - 23 - 6.6 programmable output linear regulator linear regulator 1 (reg1) t = 25 c, external transistor pnp: bc807-25 parameters test conditions min. typ. max. unit current consumption during operation idle, 50 ua current consumption during power off 1 na drop out voltage iout= 100ma 0.3 v input voltage 3.3 3.6 v programmable output voltage range iout= 100ma 3.0 3.3 v maximum output current (pnp) the characteristics vary with the associated external components (pnp). 250 ma load regulation (pnp) vin= 3.3v, vout=3.0v, iout= 1 00ma 50 mv line regulation (pnp) vin=3.3v...3.6v, vout=3.0v, iout= 100ma 50 db reg_ctrl sink current vin=3.3v, vout=3.0v*0.95 tbf ma reg_ctrl leakage current during power off vin= 3.3v, vout= tristate 0.1 ua 6.7 usb phy electronic characteristics ( 25c, vdd_usb = 3.3v, dvdd1, 3 =1.9v) parameter sym. conditions min. typ. max. unit dc supply voltage for usb ouput stage vdd_usb 3.0 3.3 3.6 v input voltage range for usb_dp/dn usb_dp usb_dn 0 vdd_usb 3.6 v input high v ih 2.0 v input low v il 0.8 ? v differential input sensitivity v di 0.2 v differential common-mode range v cm 0.8 --- 2.5 v single-end receiver threshold v se 0.8 2.0 v output low v ol 0.3 v output high v oh 2.8 v output signal cross voltage v crv 1.3 2.0 v pull-up resistor r up ? 1.2 1.5 1.8 k & driver output resistance z drv 8 12 & transceiver capacitance c in 20 pf driver rise time t r c l = 50pf 4 8 15 ns W681307 publication release date: may, 2007 revision 1.3 - 24 - driver fall time t f 4 8 15 ns rise and fall time matching t lrlf t lrlf = t lr/ t lf 90 100 111 % standby 10 na input mode 2 ma vdd_usb supply current * (exclude internal pull high resistor) i usb output mode 2 ma 6.8 usb pll electronic characteristics ( 25c, avdd = 3 .3v, dvdd1, 3 =1.9v) parameter sym. conditions min. typ. max. unit operation current i pll vco freq = 96mhz, fout freq = 48mhz ma pll shut-down current i pll_dn ua operation voltage v pll 3.0 3.3 3.6 v input clock frequency range f in 13.824 mhz comparison frequency f ref 768 khz pll output frequency f out 48 mhz vco frequency f vco --- 96 --- mhz ouput duty cycle 40 50 60 % pll short-term peak to peak output jitter t jitter ps pll lock in time t ready ms 6.9 the crystal specification requirement the below figure is shown the electrical equivalent circuit for a crystal and the parameters are used for the crystal circuit. c o = 5 . 1 p f r c = 3 0 o h m l c = 5 . 9 9 m h c c = 2 2 . 1 2 f f W681307 publication release date: may, 2007 revision 1.3 - 25 - 6.10 recommended crystal specification the following crystal specifications are recommende d for a proper cooperation between the crystal and baseband crystal oscillator. correct coordination guarantees great reliability a nd low failure rates in production. limit values parameter min. type. max. unit condition frequency 13.824 mhz fundamental mode tolerance of center frequency -10 +10 ppm 25 c 3 c tolerance over operation range -5 +5 ppm 0 c to 55 c crystal current load capacitance 18 pf dynamic capacitance cc 22.12 ff resonance resistance rc 40 electrostatic capacitance 5.1 pf aging 3 ppm/year W681307 publication release date: may, 2007 revision 1.3 - 26 - 7. memory and register map 7.1 program memory map program area memory is mapped from 0x0000 to 0xffff , this can be used by external rom. 7.2 data memory map data memory address size function comment 0x0000 - 0x0fff (4kb) not allocated 0x1000 - 0x143f (except for 0x1401 and 0x1420) (1kb) blocked for test modes (0x1401 and 0x1420 are activ ation registers) 0x1440 - 0x144f (16b) support logic 0x1450 - 0x145f (16b) interface logic 0x1460 - 0x1466 (07b) speech interface 0x1467 (01b) multiplexer to connect 5 pcm channels to 4 dsp channels 0x1468 - 0x146f (15b) fine tune gain 0x1470 - 0x1474, 0x150c (06b) (0x1475 ~ 0x147f: to be defined) processor interface (auxopport,diagsel,diag_cs,diag _cs3,multiplier_enable) 0x1480 - 0x14bf (52b) (0x1487, 0x1497, 0x149d ~ 0x149f, 0x14a7, 0x14ad ~ 0x14ae, 0x14b7, 0x14bd ~ 0x14bf: to be defined) transcoder dsp registers 0x14c0 - 0x14ff (58b) (0x14fa~ 0x14ff: to be defined) half acoustic echo canceller registers 0x1500 - 0x151f (24b) (0x1516 ~ 0x1517, 0x1519, 0x151b ~ 0x151f: to be defined) mcu system register 0x1520 - 0x157f (except for 0x1521) (96b) blocked for test modes (0x1521 is ti path selection register) 0x1580 - 0x15bf (64b) (reserved) 0x15c0 - 0x15cf (14b) (0x15c7, 0x15cf: to be defined) acoustic side / network side power measurement 0x15d0 - 0x16ff (304b) (reserved) 0x1700 ? 0x171f (11b) (0x1705 ~ 0x1707, 0x170d ~ 0x170f, 0x1711 ~ 0x171f: to be defined) pcm highway 0x1720 ? 0x1728 (9b) 0x1729 ~ 0x172f: to be defined) master or slave spi interface 0x1730 ~ 0x173f (16b) data flash spi interface 0x1740 ? 0x175f (11b) (0x174b ~ 0x175f: to be defined) w2s interface 0x1760 ? 0x177b (27b) (0x1764: to be defined) blocked for test modes 0x1800 ~ 0x187f (127) usb control registers 0x1900 ~ 0x1901 (2b) isp mode control register 0x5000 - 0x6fff (8kb) reserved for on-chip expansion 0x7000 - 0x7fff (4kb) on chip data ram *4 0x8000 - 0xefff (4-28kb) external data ram programmable selected by cs1 *2 0xf000 - 0xffff (4kb) external data ram selected by cs2 *3 *1. specific registers are blocked for test modes o f hardware logic functions. *2. the on-chip ram is contiguous with cs1, which i s used for off chip ram.cs2 is the same. *3. cs1 is a programmable address range, cs1 can be programmable range starting at 0x8000 and ending a t 0xefff, with step 4k. cs2 is the same. *4. in the event of further on chip ram being requi red this can be put in this reserved location, henc e on-chip and off chip ram will remain contiguous. the address decoding logic in this chip will not de code this area. W681307 publication release date: may, 2007 revision 1.3 - 27 - 7.3 register map 7.3.1 mixer and speech logic registers overview address name mode value at reset function 0x1401 mixer_en r/w 0x00 enable the mixer block. 0x1420 speech logic_en r/w 0x04 enable the four channels of speech logic interface (which is not needed by the codec). (0x1000 ~ 0x143f are blocked for test modes except for 0x1401 and 0x1420) 7.3.2 support logic registers overview address name mode value at reset function 0x1440 clockenable r/w 0x78 clock 3, 4 & 5 enable b its and reset 32k logic 0x1441 intrptsource0 r/w 0x00 interrupt source regi ster 0 0x1442 intrptsource1 r/w 0x00 interrupt source regi ster 1 0x1443 intrptenable0 r/w 0x00 interrupt enable regi ster 0 0x1444 intrptenable1 r/w 0x00 interrupt enable regi ster 1 0x1445 intrptpriority0 r/w 0x00 interrupt priority register 0 0x1446 intrptpriority1 r/w 0x00 interrupt priority register 1 0x1447 soundertone1 r/w 0x00 sounder frequency cont rol register 1 0x1448 soundertone2 r/w 0x00 sounder frequency cont rol register 2 0x1449 soundervol1 r/w 0x00 sounder volume control register 1 0x144a soundervol2 r/w 0x00 sounder volume control register 2 0x144b piezo function r/w 0x00 piezo enable and fre quency select 0x144c piezo clock output r/w 0x00 output the piezo driving clock 0x144d intrptsource2 r/w 0x00 interrupt source regi ster 2 0x144e intrptenable2 r/w 0x00 interrupt enable regi ster 2 0x144f intrptpriority2 r/w 0x00 interrupt priority register 2 W681307 publication release date: may, 2007 revision 1.3 - 28 - 7.3.3 interface logic registers overview address name mode value at reset function 0x1450 keyiodr r/w 0x1f - row keys io port direction control & wake up enable 0x1451 keyiodc r/w 0x1f col keys io port direction control 0x1452 keyioipr undefined row keys io port input data register 0x1453 keyioipc undefined col keys io port input data register 0x1454 keyioopr undefined row keys io port output data register 0x1455 keyioopc undefined col keys io port output data register 0x1456 keyiomskr r/w 0x00 row keys io port control register for mask 0x1457 keyiomskc r/w 0x00 col keys io port control register for mask 0x1458 keylocation r 0x00 gives the row and column numbers of the last detect ed key press 0x1459 keypadsize r/w 0x00 sets the size of the keypad scanned by the keypad s canner function 0x145a watch dog control r/w 0x00 control watchdog and keypad bounce 0x145b timer 1ms control1 r/w 0x00 control the 1ms timer 0x145c timer control r/w 0x00 reset the 1ms, 1s, 1m in timer 0x145d 1s counter r/w 0x00 second counter 0-59 0x145e watch dog kick r/w 0x00 reset the watchdog 0x145f 1ms counter r 0x00 1ms counter, reset, enabl e bit and counter value 7.3.4 speech interface registers overview address name mode value at reset function 0x1460 speech control 0 r/w 0x00 configuration register for pcm interface 0x1461 specific register r/w 0x00 blocked for test modes 0x1462 speech io direction r/w 0x00 speech i/o interface direction control 0x1463 speech io input data r/w 0x00 speech i/o port input data 0x1464 speech io output data r/w 0x00 speech i/o port output data 0x1465 speech io mask r/w 0x00 speech i/o port control register for mask 0x1466 fsync counter r/w 0x00 frame sync counter within the speech interface 0x1467 multiplexer control register r/w 0x00 multiplexer to connect 5 pcm channels to 4 dsp chan nels 0x1468 ftingain3 r/w 0x00 fine tune gain input stage 0x1469 ftoutgain3 r/w 0x00 fine tune gain output stage 0x146a ftingain2 r/w 0x00 fine tune gain input stage 0x146b ftoutgain2 r/w 0x00 fine tune gain output stage 0x146c ftingain1 r/w 0x00 fine tune gain input stage 0x146d ftoutgain1 r/w 0x00 fine tune gain output stage 0x146e ftingain0 r/w 0x00 fine tune gain input stage 0x146f ftoutgain0 r/w 0x00 fine tune gain output stage W681307 publication release date: may, 2007 revision 1.3 - 29 - 7.3.5 processor interface registers overview address name mode value at reset function 0x1470 auxopport r/w 0x00 chip selects or output po rts 0x1471 reserved 0x1472 diag_cs r/w 0x00 chip selects or output ports 0x1473 diag_cs3 r/w 0x00 chip selects or output ports 0x1474 mutiplier_enable r/w 0x00 fast 8x8 multiplier in t8032 0x1475- 0x147f reserved 7.3.6 transcoder dsp registers overview address name mode value at reset function 0x1480 connect0 r/w 0x00 specify mixing among four pcm channels 0x1481- 0x1483 specified register r/w 0x00 blocked for test modes 0x1484 pcmmode0 r/w 0x00 select between 14-bit linear, a-law and -law mode 0x1485 inputgain0 r/w 0x00 pcm input gain 0x1486 outputgain0 r/w 0x00 pcm output gain 0x1487 reserved 0x1488 tonefreqa0 r/w 0x00 set frequency of tone a 0x1489 tonefreqb0 r/w 0x00 set frequency of tone b 0x148a tonevola0 r/w 0x00 set level of tone a 0x148b tonevolb0 r/w 0x00 set level of tone b 0x148c toneena0 r/w 0x00 enable addition of tones 0x148d sidetone r/w 0x00 set sidetone gain 0x148e lookback_en r/w 0x00 test facilities for tra nscoder dsp 0x148f specified register r/w 0x00 blocked for test modes 0x1490- 0x149c connect1 ~ toneena1 r/w 0x00 the functions are the same as channel 0 0x149d? 0x149f reserved 0x14a0- 0x14ac connect2 ~ toneena2 r/w 0x00 the functions are the same as channel 0 0x14ad? 0x14ae reserved 0x14af sidetonechannel_ena r/w 0x01 side tone enables for each active pcm channel 0x14b0- 0x14bc connect3 ~ toneena3 r/w 0x00 the functions are the same as channel 0 0x14bd? 0x14bf reserved W681307 publication release date: may, 2007 revision 1.3 - 30 - 7.3.7 echo canceller registers overview address name mode value at reset function 0x14c0 up_config r/w 0x00 configuration for the echo cancellation unit 0x14c1 up_reset r/w 0x08 enables the three buffers used by the echo cancella tion fir filter 0x14c2 ec_belta r/w 0x03 the echo cancellation update gain 0x14c3 specific register r/w 0x03 blocked for test modes 0x14c4 ls_build_up_time r/w 0x07 controls acoustic suppression factor convergence to wards target 0x14c5- 0x14c6 ls_max_atten r/w 0x1ca8 maximum attenuation value that will be utilised by the acoustic suppression algorithm 0x14c7- 0x14c8 ls_min_atten r/w 0xffff minimum attenuation value that will be utilised by the acoustic suppression algorithm 0x14c9 dt_long_acoustic_atta ck_tc r/w 0x09 attack time for long term acoustic power estim ation 0x14ca dt_short_acoustic_att ack_tc r/w 0x0b attack time for short term acoustic power esti mation 0x14cb- 0x14cc dt_acoustic_hangover_ time r/w 0x0020 define the inertial delay of the double talk detect ion algorithm for acoustic side 0x14cd- 0x14ce dt_acoustic_dev_thres hold r/w 0x0666 define the instantaneous acoustic power chan ge 0x14cf- 0x14d0 dt_short_acoustic_thr eshold r/w 0x0404 define the power threshold 0x14d1 vd_long_network_atta ck_tc r/w 0x09 attack time for long term network power estima tion 0x14d2 vd_short_network_att ack_tc r/w 0x0b attack time for short term network power estim ation 0x14d3- 0x14d4 vd_network_hangover _time r/w 0x0009 define the inertial delay of the voice detection al gorithm for the network side 0x14d5- 0x14d6 vd_network_dev_thres hold r/w 0x0666 define the instantaneous network power chang e 0x14d7- 0x14d8 vd_long_network_thre shold r/w 0x0666 minimum power level that constitutes speech over th e network interface, as measured by the long term pow er estimation algorithm 0x14d9- 0x14da vd_short_network_thr eshold r/w 0x040e minimum power level that constitutes speech over th e network interface, as measured by the short term po wer estimation algorithm 0x14db- 0x14dc vd_cut_off_network_p ower r/w 0x0666 configurable bias for network power estimati on 0x14dd specific register r/w 0x00 blocked for test modes 0x14de acoustic / network active status r 0x00 acoustic side and network side active status 0x14df- 0x14e0 agc_threshold r/w 0x0800 the agc threshold is set the maximum output power f rom agc module 0x14e1- 0x14e2 agc_noise_threshold r/w 0x00c8 the calculated input power is compared with the agc_noise_threshold 0x14e3 agc_max_sg r/w 0x02 the agc module has maximum gain to amplifier the ec ho cancelled input signal 0x14e4 specific register r/w 0x0f blocked for test modes 0x14e5 agc_lg_attack_tc r/w 0x0b the field defines the inertial delay utilized for t he long term gain estimation 0x14e6 agc_st_attack_tc r/w 0x09 attack time for short term agc power estimatio n 0x14e7 ns_sttack_tcand_gain r/w 0x00 set noise_suppressor_index and shorttermpowert c 0x14e8 ns_atten_dw_up_tc r/w 0x00 set noise_rise_tc and noise_fall_tc 0x14e9 ns_active_power_msb r/w 0x00 set noise threshold 0x14ea ns_active_power_lsb r/w 0x00 set noise threshold W681307 publication release date: may, 2007 revision 1.3 - 31 - 7.3.8 soft clip registers overview address name mode value at reset function 0x14eb soft clip control r/w 0x00 enable the soft c lipping function 0x14ec vd soft clip normal index r/w 0x00 control t he gain of vd soft clip module at normal mode 0x14ed vd soft clip low index r/w 0x00 control the gain of vd soft clip module at low mode 0x14ee 0x14ef vd sc threshold r/w 0x0400 determine the selection of soft clip gain 0x14f0 shorttermprenetworkpowera ttacktc r/w 0x07 time constant use to calculate the short term netwo rk power for vd soft clip 0x14f1 vdsc attack tc r/w 0x07 smooth the gain chan ge 0x14f2 dt soft clip normal index r/w 0x00 control t he gain of dt soft clip module at normal mode 0x14f3 dt soft clip low index r/w 0x00 control the gain of dt soft-clip module at low mode 0x14f4 0x14f5 dt sc threshold r/w 0x0400 determine the selection of soft clip gain 0x14f6 shorttermpostacousticpower attacktc r/w 0x07 time constant use to calculate the short term acous tic power for dt soft clip 0x14f7 dtsc attack tc r/w 0x07 smoothing function, smooth the gain change 7.3.9 codec digital part address name mode value at reset function 0x1500 codec_onoff_scheme r/w 0x00 hardware scheme to arrange the procedure and timing for codec_digital_disable and codec_analog_disable 0x1501 codec digital part r/w 0x80 reset codec fifo value or reset codec fifo point 0x1502 codec adc abf prob r/w 0xff adaptive bit flip probability of the adc path in th e codec modulator 7.3.10 sounder path select address name mode value at reset function 0x1503 sounder path r/w 0x00 sounder signal select pdm or pwmnd reference clock generation for external melody chip 7.3.11 frequency adjustment of crystal oscillator address name mode value at reset function 0x1504 faco r/w 0x00 select the on-chip capacitance connected to xtal1 a nd xtal2 respectively 7.3.12 specific register address name mode value at reset function 0x1505 specific register r/w 0x00 blocked for test modes W681307 publication release date: may, 2007 revision 1.3 - 32 - 7.3.13 vag selection address name mode value at reset function 0x1506 vag selection r/w 0x00 select the reference voltage at pin vag. 7.3.14 codec control register overview address name mode value at reset function 0x1507 tg1 gain register r/w 0x00 set tg1 gain from 0db, 6db, 12db, 18db to 24db or b ypass and doublt you selected gain. tg2 internal gain. 0x1508 po gain register r/w 0x00 set po gain from - 4db, 2db, 8db or bypass 0x1509 codec_ctrl r/w 0x00 op amp po power down, codec analog loopback, codec transmitter gain 7.3.15 specific registers address name mode value at reset function 0x150a specific register r/w 0x00 blocked for test modes 0x150b specific register r/w 0x00 blocked for test modes 7.3.16 test cases and debugging registers overview address name mode value at reset function 0x150c receive_diag r/w 0x00 register for diagnosti c and output pins switch 0x150d specific register r/w 0x00 blocked for test modes 0x150e enallclock r/w 0x00 enable all of test clock 0x150f codec_test_sel r/w 0x00 digital codec part t est mode selection 0x1510 rssi mode r/w 0x00 use for isp mode protect 0x1511 bgp_lpf_en r/w 0x00 enable the low pass filt er at the bgp generator 0x1512 codec status indicator r/w 0x00 codec dac ad c fifo point indicator 0x1513 bandgap voltage adjustment r/w 0x00 bandgap voltage adjustment 0x1514 specific register r/w 0x00 blocked for test modes 0x1515 linear regulator voltage controller register r/w 0x00 the adjustment possibilities of output voltage of t he linear regulator have been built in to compensate the band gap variation in process. 0x1516- 0x1517 reserved 7.3.17 charge park detection address name mode value at reset function 0x1518 core pwr_det r 0x00 monitor core power voltage W681307 publication release date: may, 2007 revision 1.3 - 33 - 7.3.18 da high pass filter selection address name mode value at reset function 0x151a da high pass filter selection r/w 0x00 codec d/a high pass filter control register W681307 publication release date: may, 2007 revision 1.3 - 34 - 7.3.19 ti path selection address name mode value at reset function 0x1521 ti path selection r/w 0x00 choose the signal to be processed in off-hook or on -hook signalling (0x1520 ~ 0x157f are bloked for test modes except f or 0x1521) 7.3.20 network side / acoustic side power measurement address name mode value at reset function 0x15c0~ 0x15c1 acoustic_short_term_ power r 0x0000 short term acoustic power calculated by the double talk detector (dt) 0x15c2~ 0x15c3 acoustic_long_term_ power r 0x0000 long term power on acoustic estimated by the double talk detector (dt) 0x15c4~ 0x15c5 acoustic_power_devi ation r 0x0000 acoustic power deviation estimated by the double ta lk detector (dt) 0x15c6 acoustic / network active status r 0x00 acoustic and network active status 0x15c7 reserved 0x15c8~ 0x15c9 network_short_term_ power r 0x0000 short term network power calculated by the voice de tector (vd) 0x15ca~ 0x15cb network_long_term_ power r 0x0000 long term power on network estimated by the voice detector (vd) 0x15cc~ 0x15cd network_power_devi ation r 0x0000 network power deviation estimated by the voice dete ctor (vd) 0x15ce acoustic / network active status r 0x00 acoustic and network active status W681307 publication release date: may, 2007 revision 1.3 - 35 - 7.3.21 pcm highway channel registers overview address name mode value at reset function 0x1700 pcm channel format and delay control of 1st group r/w 0x02 pcm channel format and delay control of 1st group i n the 1st pcm highway 0x1701 tx delay1 r/w 0x00 set the values for delaying the transmitted bits of pcm channel1 after the rising edge of the fsync. 0x1702 tx delay2 r/w 0x00 set the values for delaying the transmitted bits of pcm channel2 after the tail bit of pcm channel 1. 0x1703 rx delay1 r/w 0x00 set the values for delaying the received bits of pc m channel1 after the rising edge of the fsync. 0x1704 rx delay2 r/w 0x00 set the values for delaying the received bits of pc m channel2 after the tail bit of rx pcm channel 1. 0x1705~ 0x1707 reserved 0x1708 pcm channel format and delay control of 2nd group r/w 0x02 pcm channel format and delay control of 2nd group i n the 1st pcm highway 0x1709 tx delay3 r/w 0x00 set the values for delaying the transmitted bits of pcm channel3 after the tail bit of pcm channel 2. 0x170a tx delay4 r/w 0x00 set the values for delaying the transmitted bits of pcm channel4 after the tail bit of pcm channel 3. 0x170b rx delay3 r/w 0x00 set the values for delaying the received bits of pc m channel3 after the tail bit of rx pcm channel 2. 0x170c rx delay4 r/w 0x00 set the values for delaying the received bits of pc m channel4 after the tail bit of rx pcm channel 3. 0x170d~ 0x170f reserved 0x1710 pcm channel format control of 2nd pcm highway r/w 0x02 pcm channel format control of the 2nd pcm highway. 7.3.22 spi interface registers overview address name mode value at reset function 0x1720 spi_control0 r/w 0x00 setting spi interface control register. 0x1721 spi_control1 r/w 0x00 setting spi interface control register. 0x1722 spi status r 0x00 read the spi status. 0x1723 spi interrupt enable r/w 0x00 enable spi int errupt. 0x1724 dumpbyte r 0x00 show the received byte when 1720[3] is set. 0x1725 write tx fifo w 0x00 store data in spi tx-fifo when micro controller wri tes data to this register. 0x1726 read rx fifo r 0x00 read data from spi rx-fifo when micro controller re ad data from this register. 0x1727 spi_transfer_size r/w 0x00 setting the trans fer size when tx and rx. 0x1728 spi_start_rtx r/w 0x00 start to transmit at the rate of transfer size when tx and rx. W681307 publication release date: may, 2007 revision 1.3 - 36 - 7.3.23 data flash spi interface registers overview address name mode value at reset function 0x1730 df_clk r/w 0x00 setting data flash spi inter face enable and clock rate. 0x1731 df_cmd_len r/w 0x00 setting data flash spi interface command length con trol register. 0x1732 df_data_len rw 0x00 setting data flash spi i nterface data length control register. 0x1733 df_intr_reg r/w 0x00 enable data flash spi interrupt. 0x1734 ~ 0x1738 df_cmd_b1 ~ df_cmd b5 rw 0x00 setting data flash spi interface command co ntact register. 0x173b df_clk_format rw 0x00 setting the data flash spi interface format . 0x173c df_fifo_data rw 0x00 read/write the data from the data flash spi interface fifo. 0x173d df_cnt r 0x00 current the data flash spi interface fifo co unter value. 0x173e df_wr_cnt r/w 0x00 cpu current write-point for the data flash spi interface fifo. 0x173f df_rd_cnt r/w 00 cpu current read-point for the data flash sp i interface fifo. 7.3.24 w2s interface registers overview address name mode value at reset function 0x1740 w2s_enable r/w 0x00 enable w2s interface. 0x1741 eeprom_config r/w 0x00 setting the page mode of eeprom. 0x1742 prescale_lo r/w 0x00 control w2s bus speed. 0x1743 prescale_hi r/w 0x00 control w2s bus speed. 0x1744 rdwrfifo r/w 0x00 read /write data into tx f ifo. 0x1745 force_activity r/w 0x00 force activities of w2s. 0x1746 w2s_status r 0x00 read w2s status. 0x1747 fifordptr r 0x00 monitor w2s fifo read point er. 0x1748 fifowrptr r 0x00 monitor w2s fifo write poin ter. 0x1749 forceackfail r/w 0x00 enable ack fail event. 0x174a w2s_misc r 0x00 monitor current finite state and interrupt indication. W681307 publication release date: may, 2007 revision 1.3 - 37 - 7.3.25 usb control registers overview address name mode value at reset function 0x1800 usb enable register r/w 00 usb 1.1 function enables control register. 0x1801~ 0x1803 usb interrupt register a. enable, status and clear r/w 00 usb endpoints interrupt enable, status and c lear. 0x1804 ~ 0x1806 usb interrupt register b. enable, status and clear r/w 00 usb endpoints interrupt enable, status and c lear. 0x1810 endpoint 0 ? control in/out registers r/w 00 control in/out endpoint control register. 0x1811 control in data r/w 00 control in endpont data. internal fifo has 8 bytes for control in transmission. 0x1820 ~ 0x1827 control hid out data r 00 control hid out receiving data. 0x1828 ~ 0x182f control out data r 00 control out endpoint receiving data. 0x1830 endpoint 1 and 2 ? iso in/out registers r/w 00 iso in/out endpoint control register. 0x1839 ~ 0x1847 iso sync speed register r/w xx iso sync fine-tuning speed parameter registe r. 0x1848 endpoint 3 ? bulk in registers-- control register r/w 00 bulk in endpoint control register 0x1849 bulk in data w 00 bulk_in transmission data register except final dat a. 0x184a bulk in final data w 00 bulk_in transmission final data register. 0x184b bulk in fifo empty flag r 00 bulk_in transmission fifo data empty flag. 0x1850 endpoint 4 ? bulk out registers--- control register r/w 00 bulk out endpoint control register 0x1851 bulk out fifo length r 00 shown bulk out endpoint receiving fifo data le ngth. 0x1852 bulk out data r 00 bulk out endpoint receiving fifo data. 0x1858 endpoint 5 ? interrupt in registers--- control register r/w 00 interrupt in endpoint control register 0x1859 usb interrupt data length r/w 00 interrupt in endpoint transmission data leng th 0x1860~0x 186f interrupt in data r/w 00 total 16 bytes interrupt in transmission dat a registers. 0x1870- 0x1874 specific register r/w 00 blocked for test modes 0x1875 specific register r/w 00 blocked for test modes W681307 publication release date: may, 2007 revision 1.3 - 38 - 7.3.26 isp mode address name mode value at reset function 0x1900 isp control register r/w 00 isp mode control and enable register 0x1901 specific register r/w 00 blocked for test modes W681307 publication release date: may, 2007 revision 1.3 - 39 - 8. support logic the support logic provides the following functional ity ? system reset and clock control ? interrupt processing / control ? ringer tone generation figure 8-1 illustrates the functionality of the mcu chip support logic reset & clock control sysclock resetn sysclock2en sysclock3en sysclock4en sysreset reset32k sysclock1 sysclock2 sysclock3 sysclock4 reset & clock control sysclock4 sysreset soundertone1 soundertone2 soundervol1 soundervol2 sndr interrupt control keyintrpt timerintrpt speechintrpt intrptsource intrptenable intrptpriority int0 int1 figure 8-1 illustration of the mcu chip support l ogic W681307 publication release date: may, 2007 revision 1.3 - 40 - 8.1 clock control & reset 32k 8.1.1 overview each register in the speech processo r support and interface logic is reset synchronously. the reset & clock control function ensures that the system reset signal is correctly g enerated. the system reset signal is also used to e nsure that bi-directional signals are all set to input during initialization. a separate rese t signal is provided for registers operating at 32k hz. the mcu chip has five internal 13.824 mhz clocks. the clocks are gated to conserve power. four clocks are of the same phase and should be balanced during layout to allow data to be handled between the clock domains without add itional logic. the clock to the 8032turbo is of the opposite phase to the other fou r 13.824mhz clocks. the 32khz clock is not gated or controlled on-chip. 8.1.2 functionality the system reset signal sysreset is used to synchronously reset all the latches, which run from the 13.824mhz system clock: ? two asynchronous latches sample the reset input. th ese are clocked to the non-reset state when the sys tem clock is running and are used to ensure that the device is reset if the system clock is not running when the reset input is released. ? all gated clocks are enabled and the sysreset signa l is asserted for 4 system clock cycles after the e nd of the external reset signal is detected by the asynchronous latches. ? sysreset is asserted from the time the asynchronous latches are reset until the end of the reset seque nce to ensure bi-directional signals are forced to safe values during initializa tion. a separate latch, controlled by a processor regist er bit reset32k holds all 32768hz logic in reset un til set by the processor. the 8032t is reset by sysreset. clock gating is performed with an o r function such that the clock signal is held high when disabled. the support and interface logic use 6 clocks: - ? sysclock: non-gated 13.824mhz clock. ? sysclock1: clock to the 8032turbo.this clock is inv erted relative to the other four sysclocks. enabled for (clocks_unstable=0). ? sysclock2: clock to the processor-writeable registe rs. controlled by the processor interface. ? sysclock3: clock to the speech interface logic (whi ch is not needed by the codec). controlled by proce ssor-writeable register. ? sysclock4: clock to the ringer tone generator. cont rolled by processor-writeable register. ? sysclock5:clock to the winbond linear codec (and lo gic in the speech interface needed to support opera tion of the codec) care will be required in the physica l design of the support logic to ensure balancing o f all clocks. all outputs from logic in the 32768hz clock domain are re-timed on entering the 13.824mhz clock domain . this is done using serial pairs of latches to give metastability protection. signals in interface logic are re-timed: - ? keypress interrupt ? watchdog interrupt ? watchdog kick ? 1 millisecond timer interrupt ? 1 second timer interrupt 8.1.3 clock enable register address access mode value at reset nominal value 0x1440 r/w 0xfd bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset32k blocked (for test modes) sysclock5en sysclock4en sysclock3en sysclock3en when set, enable system clock 3. W681307 publication release date: may, 2007 revision 1.3 - 41 - sysclock4en when set, enable system clock 4. sysclock5en when set, enable system clock 5. reset32k set low to reset the 32khz clock source. 8.2 interrupt control 8.2.1 overview the support and interface logic generate internal e vents, these interrupt events are conditioned by th e interrupt control logic before it is issued to the processor. figure 8-2 shows the inte rrupt structure. 8.2.2 functionality the support and interface logic generate interrupt events as one-cycle pulses. the support and interfa ce logic generate the following interrupts: ? hardware keypad scanner interrupt ? keypad port input general purpose io interrupt ? timer interrupt ? speech interface interrupt ? watchdog interrupt the speech interface generates the following interr upts: - ? pcm port input general purpose io interrupt three registers control the generation of interrupt s in the mcu chip, the intrptsource register, the i ntrptenable register and the intrptpriority register. each interrupt has a corre sponding bit in the intrptsource, intrptenable and intrptpriority registers. ? the intrptsource register is set when an interrupt event occurs and is cleared by processor write. ? when the processor writes to intrptsource, any bits that are set to 1 cause the corresponding bit of i ntrptsource to be cleared, bits set to 0 are not affected. ? an interrupt is generated when intrptsource and int rptenable =1 for any of the interrupt sources. ? for each bit; if intrptpriority =0, the interrupt i s issued to int0, if intrptpriority =1, the interru pt is issued to int1. ? the watchdog interrupt is implemented for debug pur poses only. the watchdog must be kicked before atte mpting to clear its associated source register. W681307 publication release date: may, 2007 revision 1.3 - 42 - interrupt source interrupt enable & & & interrupt priority interrupt registers int0 int1 figure 8-2 interrupt structure W681307 publication release date: may, 2007 revision 1.3 - 43 - 8.2.3 interrupt registers address name description bit description value at reset 0 blocked(for test modes) 0 1 blocked(for test modes) 0 2 blocked(for test modes) 0 3 blocked(for test modes) 0 4 blocked(for test modes) 0 5 timer1sintrpt 0 6 timer1msintrpt 0 1441h intrptsource0 interrupt source register 0 read: 1 = interrupt 0 = no interrupt write: 1 = clear 7 keypressintrpt 0 0 speechiointrpt 0 1 watchdogintrpt 0 2 keyiointrpt 0 3 blocked(for test modes) 0 4 blocked(for test modes) 0 5 blocked(for test modes) 0 6 blocked(for test modes) 0 1442h intrptsource1 interrupt source register 1 read: 1 = interrupt 0 = no interrupt write: 1 = clear 7 blocked(for test modes) 0 0 blocked(for test modes) 0 1 blocked(for test modes) 0 2 blocked(for test modes) 0 3 blocked(for test modes) 0 4 blocked(for test modes) 0 5 timer1sintrpt 0 6 timer1msintrpt 0 1443h intrptenable0 interrupt enable register 0 1 = enabled 0 = disabled 7 keypressintrpt 0 0 speechiointrpt 0 1 watchdogintrpt 0 2 keyiointrpt 0 3 blocked(for test modes) 0 4 blocked(for test modes) 0 5 blocked(for test modes) 0 6 blocked(for test modes) 0 1444h intrptenable1 interrupt enable register 1 1 = enabled 0 = disabled 7 blocked(for test modes) 0 0 blocked(for test modes) 0 1 blocked(for test modes) 0 2 blocked(for test modes) 0 3 blocked(for test modes) 0 4 blocked(for test modes) 0 5 timer1sintrpt 0 6 timer1msintrpt 0 1445h intrptpriority0 interrupt priority register 0 0 = int0 1 = int1 7 keypressintrpt 0 0 speechiointrpt 0 1 watchdogintrpt 0 2 keyiointrpt 0 3 blocked(for test modes) 0 4 blocked(for test modes) 0 5 blocked(for test modes) 0 6 blocked(for test modes) 0 1446h intrptpriority1 interrupt priority register 1 0 = int0 1 = int1 7 blocked(for test modes) 0 W681307 publication release date: may, 2007 revision 1.3 - 44 - 8.2.4 extends of interrupt 0 blocked(for test modes) 0 1 reserved 0 2 spiintrpt 0 3 w2sintrpt 0 4 blocked(for test modes) 0 5 cpwrintrpt 0 6 reserved 0 144dh intrptsource2 interrupt source register 2 1 = interrupt 0 = cleared 7 usbintrpt 0 0 blocked(for test modes) 0 1 reserved 0 2 spiintrpt 0 3 w2sintrpt 0 4 blocked(for test modes) 0 5 cpwrintrpt 0 6 reserved 0 144eh intrptenable2 interrupt enable register 2 1 = enable 0 = disable 7 usbintrpt 0 0 blocked(for test modes) 0 1 reserved 0 2 spiintrpt 0 3 w2sintrpt 0 4 blocked(for test modes) 0 5 cpwrintrpt 0 6 reserved 0 144fh intrptpriority2 interrupt priority register 2 0 = int0 1 = int1 7 usbintrpt 0 W681307 publication release date: may, 2007 revision 1.3 - 45 - 8.3 ringer tone generator 8.3.1 overview the buzzer signal generates tones to signal an inco ming call. there are two buzzer signal can be selected to conn ect to sndr pin. this subsection describes the ring er tone generator with the pwm (pulse width modulation) format. the other buzzer s ignal of pdm (pulse density modulation) format will be described on 1503[1:0]. 8.3.2 functionality /16 /n /32 decoder /16 /n /32 decoder 864khz 864khz soundertone1 soundertone2 soundervol1 soundervol2 sysclk sysclk 3388hz to 864khz 3388hz to 864khz 105hz to 27khz 105hz to 27khz sounder figure 8-3 the ringer tone generator the ringer tone generator has two controllable tone sources, shown in figure 8-3. this each gives a pr ogrammable output frequency of between 105hz and 27khz. each tone source has a pro grammable mark-to-space ratio. by controlling the m ark to space ratio the volume of the sounder can be controlled. ? the 16 function produces a 864khz pulse from the 13.824 mhz system clock. ? the n function produces a 3388 to 864khz pulse from its 864khz input. the output frequency of this functio n and the corresponding output frequency of the chip is deter mined by the soundertone register. ? the 32 function contains a counter, clocked by the sys tem clock, which increments on each pulse at it inp ut. the decoder uses the 4-bit output from this counter to produce a 105hz to 27khz with a programmable mark-space rat io defined by the soundervol register. ? the tone source always starts in the same way (for a given set of programmed values) ? the tone source stops cleanly, that is it stops in the inactive state (logic 0) without truncation of any ongoing high pulse. ? the results of tone source one and tone source two are logically or together to produce the output sig nal sounder?. ? both tone generators have a common enable signal to allow them to be synchronized together. ? W681307 publication release date: may, 2007 revision 1.3 - 46 - 8.3.3 sounder tone register definition the registers soundertone1 and soundertone2 set the output frequency of the corresponding tone generat or. each 8-bit register has a range of 1 to 255 (decima l) corresponding to an output frequency range of 10 5hz to 27khz, with a 10% tolerance. 8.3.4 sounder volume register definition the registers soundervol1 and soundervol2 set the m ark to space register of the corresponding tone gen erator. table 8-1: soundervol1 and soundervol2 pulse genera tion ratio. bit 4 bit 3 bit 2 bit 1 bit 0 mark space 0 0 0 0 0 no output (permanent low) 0 0 0 0 1 1 31 0 0 0 1 0 2 30 0 0 0 1 1 3 29 0 0 1 0 0 4 28 0 0 1 0 1 5 27 0 0 1 1 0 6 26 0 0 1 1 1 7 25 ???? 1 1 1 1 0 30 2 1 1 1 1 1 31 1 8.3.5 example of use in order to generate a 794hz frequency output from tone source one with a mark to space ratio of 1:1. program the soundertone1 register with 00100010 ( n = 35) and program the soundervol1 register with 10000. to give a 1350hz frequency output from tone source one with a mark to space ratio of 7:25. program the soundertone1 register with 00010100 ( n = 21) and program the soundervol1 register with 00111. W681307 publication release date: may, 2007 revision 1.3 - 47 - 8.3.6 sounder registers address name description bit description value at reset 0 0 1 0 2 0 3 0 4 0 5 0 6 0 1447h soundertone1 sounder frequency control 7 sounder frequency control 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 1448h soundertone2 sounder frequency control 7 sounder frequency control 0 0 0 1 0 2 0 3 0 4 sounder volume control 0 5 reserved 0 6 reserved 0 1449h soundervol1 sounder volume control 7 tone generators enable = 1 0 0 0 1 0 2 0 3 0 4 sounder volume control 0 5 reserved 0 6 reserved 0 144ah soundervol2 sounder volume control 7 tone generators enable = 1 0 0 enable 0 1 frequency select 0: 216khz, 1: 108khz 0 2 reserved 0 3 reserved 0 4 reserved 0 5 reserved 0 6 reserved 0 144bh piezo function enable piezo function select piezo frequency 7 reserved 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 144ch piezo clock output output twice clock count of this register value 7 piezo driving signal from pcm0 0 W681307 publication release date: may, 2007 revision 1.3 - 48 - 8.4 piezo tone generator 8.4.1 overview the piezo signal can generated by the ringer tone g enerator, this subsection describe the piezo-drivin g clock from the ringer tone generator, shown in figure 8-4. 8.4.2 functionality vcc inductor r diode r r piezo pcm1/rt0 sndr c figure 8-4 piezo tone circuit the pcm1/rto pin generates the driving signal to ob tain higher voltage. when set register 0x144b[0], w ill enable the functionality of piezo, 0x144b[1] select the frequency of 108khz or 216khz for driving signal. the register 0x144c[7:0] output the twice number of clock for up conversion the voltage. the sounderton e and soundervol register controls the melody of pi ezo. W681307 publication release date: may, 2007 revision 1.3 - 49 - 9. interface logic the interface logic consists of ? a keypad scanner ? timers ? input/output ports figure 9-1 illustrates the operation of the interfa ce logic keypad scanner state machine io register /256 125hz 32000hz unstable_ck13m intwritedata[7..0] ioreaddata ioreadvalid intaddress [9.. 0 ] keyintrpt timerintrpt dogtimeout keyrox[5:0] keyro[6..0] keyrd [6..0] keyco [6..0] keycd [6..0] / 32 /1000 1ms 100hz timer 32khz keyrix[5:0] keycix[4:0] keycix[5:0] figure 9-1 the interface logic. 9.1 keypad scanner 9.1.1 overview the keypad scanner state machine operates from the 32000hz clock. the keypad scanner identifies which key has been pressed and includes de-bouncing logic. multiple concurrent key presses are not supported. dividers provide 1hz an d 1ms timing signals. the 1 hz signal provides timing for keypad de-bouncing and t he 1 hz and 1ms signals are used for the timer. the keysize register sets the size of the keypad, u p to 9 of the unused signals can be used as io port s. all active row outputs are initially set high, each column input has an external pull-down resistor. w hen a key is pressed, the signal from one column will go high. the keypad scanner fu nction operates as follows: ? the state machine waits in a default state until a high is found at one of the column inputs. ? each active row output is set low in turn until a l ow is detected at the column input. the row and col umn numbers are stored. ? the state machine waits for the de-bounce period se t in the keybounce register. ? each row output is set low in turn until a low is d etected at the column input. the row and column num bers are stored. ? the row and column numbers stored at 2 and 4 are co mpared. if these are the same, a valid keystroke ha s been detected. ? the state machine waits for unstable_ck13m to go lo w, asserts keyintrpt and returns to 1. the keybounce register sets a de-bounce period of 8 ms, 16ms, 24ms or 32ms (times are -0.0 ms +1.5 ms). W681307 publication release date: may, 2007 revision 1.3 - 50 - 9.1.2 use of the keypad scanner the software should set up the keypadsize register so that the keypad can be used. this register sets the keypad size and the de-bounce period. once a key has been de-bounced a keyintrpt interrup t is generated and the key value is stored in the k eylocation register. when the key is released a further keyintrpt interrupt is genera ted. (note that only two interrupts are generated i n a key press release sequence and that holding a key down for extended periods does not re sult in multiple interrupts.) the keypress register bit in the keylocation states whether a key is pressed. when a key is pressed th e bit is active once the key press has been de-bounced and is removed once the key is released. where ports are being used with the hardware keypad scanner, the corresponding data bit in the key io port output data register must be set to zero. 9.1.3 use of a software keypad scanner if keypad scanning is done in software than the key pad scanner functionality is not used and the pins are treated as general purpose i/o ports keyc[3:0] and keyr[4:0]. 9.2 i/o ports pins not used by the keypad scanner are available a s standard io ports, controlled by keyiodr, keyiodc , keyioipr, keyioipc, keyioopr and keyioopc. an interrupt event will be g enerated if there is a change in the value of any o ne of keyioip and the corresponding bit of keyiomsk is set. note that the direction of keyc[3:0] amd keyr[4:0] are always controlled by the keyiodc[3:0], keyiodr[ 4:0] registers. W681307 publication release date: may, 2007 revision 1.3 - 51 - 9.3 keypad control registers address name description bit description value at reset physical mapping to output ports 0 keyiodr[0] 1 row[0] 1 keyiodr[1] 1 row[1] 2 keyiodr[2] 1 row[2] 3 keyiodr[3] 1 row[3] 4 keyiodr[4] 1 row[4] 5 reserved 1 6 blocked (for test modes) 0 1450h keyiodr sysclock2 key io port direction control register 0 = output 1 = input(default) 7 reserved 1 0 keyiodc[0] 1 col[0] 1 keyiodc[1] 1 col[1] 2 keyiodc[2] 1 col[2] 3 keyiodc[3] 1 col[3] 4 reserved 1 5 reserved 1 6 reserved 1 1451h keyiodc sysclock2 key io port direction control register 0 = output 1 = input 7 reserved 1 0 keyioir[0] 0 row[0] 1 keyioir[1] 0 row[1] 2 keyioir[2] 0 row[2] 3 keyioir[3] 0 row[3] 4 keyioir[4] 0 row[4] 5 reserved 0 6 reserved 0 1452h keyioipr sysclock2 key io port input data register value =true 7 reserved 0 0 keyioic[0] 0 col[0] 1 keyioic[1] 0 col[1] 2 keyioic[2] 0 col[2] 3 keyioic[3] 0 col[3] 4 reserved 0 5 reserved 0 6 reserved 0 1453h keyioipc sysclock2 key io port input data register value =true 7 reserved 0 0 keyioor[0] 0 row[0] 1 keyioor[1] 0 row[1] 2 keyioor[2] 0 row[2] 3 keyioor[3] 0 row[3] 4 keyioor[4] 0 row[4] 5 reserved 0 6 reserved 0 1454h keyioopr sysclock2 key io port output data register value =true 7 reserved 0 W681307 publication release date: may, 2007 revision 1.3 - 52 - address name description bit description value at reset physical mapping to output ports 0 keyiooc[0] 0 col[0] 1 keyiooc[1] 0 col[1] 2 keyiooc[2] 0 col[2] 3 keyiooc[3] 0 col[3] 4 reserved 0 5 reserved 0 6 reserved 0 1455h keyioopc sysclock2 key io port output data register value =true 7 reserved 0 0 keyiom[0] 0 row[0] 1 keyiom[1] 0 row[1] 2 keyiom[2] 0 row[2] 3 keyiom[3] 0 row[3] 4 keyiom[4] 0 row[4] 5 reserved 0 6 reserved 0 1456h keyiomskr sysclock2 key io port control register for mask 0= off=masked 1= on=unmasked 7 reserved 0 0 keyiom[0] 0 col[0] 1 keyiom[1] 0 col[1] 2 keyiom[2] 0 col[2] 3 keyiom[3] 0 col[3] 4 reserved 0 5 reserved 0 6 reserved 0 1457h keyiomskc sysclock2 key io port control register for mask 0=off=masked 1=on=unmasked 7 reserved 0 0 keylocr[0] 0 1 keylocr[1] 0 2 keylocr[2] 0 3 keylocc[0] 0 4 keylocc[1] 0 gives the row and column 5 keylocc[2] 0 shows ?1? when keypad is pressed 6 keypressed 0 1458h keypress location read only 7 reserved 0 0 keyrows[0] 0 1 keyrows[1] 0 2 keyrows[2] 0 3 keycolumn[0] 0 4 keycolumn[1] 0 5 keycolumn[2] 0 6 keydb[0] 0 1459h keypadsize sets the size of the keypad scanned by the keypad scanner function 7 keydb[1] 0 the timer1sreset bit and watchdog time bits cannot be altered once the watchdog is enabled. the watchdog is reset every time the location watch dogkick is written to. W681307 publication release date: may, 2007 revision 1.3 - 53 - 9.3.1 key location and size programming key location and size registers, keylocr[*], keyloc c[*], keyrows[*] & keycolumns[*] are defined as fol lows:- row/column [2:0] zero (see note) 0x00 one 0x01 two 0x02 three 0x03 four 0x04 five 0x05 note: that zero is only valid for keyrows[*] and keycolum ns[*], which means the keypad size=0 and all the ke ypad pins serve as gpio. on the other hand, the keylocr[*] and keylocr[*] are o nly checked when keypressed bit=1 (0x1458[7]) and m eanwhile it should contain non-zero value. 9.4 timers there are 3 timers: - ? a programmable 1-millisecond timer ? a 1 second timer ? a programmable 1-second watchdog timer. the programmable 1-millisecond timer can be enabled , reset and programmed to generate an pulse in the range 1 millisecond to 64 milliseconds (1 millisecond spacing). the 1-second timer can be enabled, reset and always generates a pulse every 1 second. the programmable 1 second watchdog timer can be ena bled and programmed to generate a pulse in the rang e 1 second to 8 seconds (1 second spacing). following reset the watchdog timer is disabled. in normal operation the watchdog timer should be en abled by writing to the watchdogenable bit and the watchdogreseten bit. once written to these bits cannot be cleared except by a system reset, hence the watchdog cannot be disable d. enabling the watchdog timer also prevents disabling of the 1-second timer. the watchdog counts from the output of the 1-second timer. the expiry time is programmable and this va lue is set in the watchdogtime[0:2] register field. the software must clear the watchdog counter regularly. if the watch dog counter ever reaches the expiry time, a reset and interrupt will occur. note: a write to the watchdogkick location will not affect the 1-second timer from which the watchdog operates. therefore if the watchdog is set to 8 seconds, the timeout will occu r between 7 to 8 seconds. the watchdogkick location must be written to before 7 seconds, otherwise a reset and interrupt will occur . it is recommended that a setting of 1 second is n ot used. in order to facilitate software debug the device ha s the watchdog expiry generated reset disabled from reset. a watchdog interrupt is provided to assist software debugging, this interru pt watchdogintrpt is generated by the watchdog time r if it expires. in this case the watchdogenable bit would be set, but not the watchd ogreseten bit. W681307 publication release date: may, 2007 revision 1.3 - 54 - 9.4.1 watch dog control address access mode value at reset nominal value 0x145a r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved watchdog reseten watch dog timer [2:0] watchdogen keybounce[1:0] watchdogen when set, enable the watchdog, which use system clock source 2. watchdogtimer [2:0] controls the repetition rate of the watchdog timer 1 second to 8 seconds. watchdogreseten when set, it will reset whole baseb and chip. keybounce[1:0] key debounce period selection. the de-bounce period is defined as follows: key-bounce period keybounce[1:0] 8 ms 0x00 16 ms 0x01 24 ms 0x02 32 ms 0x03 all times are +/- 0.5ms 9.4.2 timer 1ms control1 address access mode value at reset nominal value 0x145b r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 timer1mslength[5:0] timer1msen timer1ms reset timer1mslength[5:0] 1ms timer counter, which contro ls the repetition rate of the 1ms timer up to 64 ms . timer1msen when set to ?1?, enable 1ms timer to pro ceed from it?s previous status. when reset to ?0?, this just pause the operation but not reset the content. timer1msreset when reset to ?0?, reset the 1ms time r. this timer will operate only when this bit remai ns ?1?. 9.4.3 timer control address access mode value at reset nominal value 0x145c r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reset 1s counter reserved reserved reset 1ms counter reset 1s timer 1s timer reset when reset to ?0?, reset the 1s time r. 1ms counter reset when reset to ?0?, reset the 1ms counter, but this bit does not affect the operation of 1ms timer which is controlled by 0x145b. 1s counter reset when reset to ?0?, reset the 1s co unter value in 0x145d, but this bit does not affect the operation of 1s timer. W681307 publication release date: may, 2007 revision 1.3 - 55 - 9.4.4 1s counter address access mode value at reset nominal value 0x145d r 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved 1s counter 1-second counter this register records the time in 1 second resolution. maximum value is 59. 9.4.5 watch dog kick address access mode value at reset nominal value 0x145e r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 watch dog kick write to this value will reset the watchdog timer. 9.4.6 1ms counter address access mode value at reset nominal value 0x145f r 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 counter value for 1ms timer this register records the time in 1 ms resolution. maximum value is 255. 1ms timer 1min counter = 1s counter 0x145d ( 0 ~ 59 sec ) 1s timer 1ms counter 0x145f ( 0~255 ms ) 1 ms 1s 0x145b[7:2] ( 0~timer1mslength[5:0]) 1ms int 1s int reset :145c[4] reset :145c[1] reset :145c[0] reset :145b[0] enable: 145b[1] syscl k note1: all the reset activities are level_triggered . note2: reset 145c[1] will not effect the waveform o f 1ms int. comparetor counter for 1ms interval int W681307 publication release date: may, 2007 revision 1.3 - 56 - 10. speech interface 10.1 overview the speech interface allows the mcu chip to be conn ected to one or more of the following: ? external pcm codec and echo canceller. ? io ports which can be used when the external speech expansion interface is not required. ? a test interface to and from the on-chip linear cod ec. the speech interface block also connects with the o n-chip linear codec. the speech interface also contains three programmab le outputs, which are used to control certain pins. 10.2 functionality figure 10-1 shows the speech interface block diagra m. speech processor interface pcmi[5] pcmo[5] pcmd[5] pcm serial interface (pcmout0) speech interface register intwritedata[7..0] spreaddata[7:0] intaddress[9..0] spreadvalid (pcmin0/pcmclocki) (pcmin1) sysclock3 sysclock2 speechintrpt p c m 0 o u t [ 1 3 : 0 ] p c m 1 o u t [ 1 3 : 0 ] p c m 2 o u t [ 1 3 : 0 ] p c m 0 i n [ 1 3 : 0 ] p c m 1 i n [ 1 3 : 0 ] p c m 2 i n [ 1 3 : 0 ] a d p c m _ c o u n t [ 7 : 0 ] a d p c m _ c l o c k sysclock3 sysclock2 speechctrl0 speechctrl1 speechiod speechioip speechioop speechiomsk pcmi[0] pcmi[1] pcmo[1] pcmd[1] pcmi[2] pcmo[2] pcmd[2] pcmi[3] pcmo[3] pcmd[3] pcmi[4] pcmo[4] pcmd[4] (pcmout1) (pcmclock) (pcmsynco) d i s h p o v c l k r e f 8 k t x m u t e a d r d d a w r r e f 3 2 k d f a i n [ 1 3 : 0 ] d m d [ 1 3 : 0 ] on chip codec interface r a d c t r l [ 3 : 0 ] sysclock5 s y s c l o c k 5 figure 10-1 speech interface block diagram W681307 publication release date: may, 2007 revision 1.3 - 57 - 10.3 pcm serial interface the pcm serial interface ? formats parallel pcm data to/from the speech proces sor for use by external devices ? pcm serial interface supports to convert serial pcm data of external devices to parallel pcm data of s peech processor. pcm highway supports 4 external devices by 4 slots pcm channels (b1 ~ b4). the internal usb iso endpoint a nd the 4 th slot of pcm highway are shared with the same pcm channel (b4). when the usb_en bit is set to high, the internal us b iso endpoint will be automatically connected to the pcm channel (b4). all channels supports 8/16 bits pcm format, and io m2 mode. ? pcm highway interface can support maste or slave mo des with external devices. ? implements a 4-bit general purpose io port when the pcm serial interface function is not required routing diagram as below figure 10-2 serial/parallel figure 10-2 W681307 speech flow block diagram 10.3.1 use with additional external lines the pcm serial interface block can route channels 1 , 2 and 3 from the speech processor to pcm highway which can be used to interface to external codecs to provide connection to two ext ernal lines. for this mode pcmif enable =1 and slave mode =0. pcm serial interface can generate a long frame sync (for longsync =1) or a short frame sync (for longs ync=0). timing diagrams for short frame sync and long frame sync modes are given in section 9.7. 10.3.2 i/o ports for pcmh1_dis =1, the speech interface is reset and pcm highway (pins name: pcm_out, pcm_in, pcm_fsc, pcm_clk) oper ate as standard io ports, controlled by speechiod, spee chioip and speechioop registers. an interrupt event will be generated if there is a change in the value of any one of speechioip and th e corresponding bit of speechiomsk is set. for pcmh1_dis=0, the direction of pcm highway is al ways controlled by the pcm highway function setting . in the pcm master mode, the pcm_out, pcm_fsc and pcm_clk pins areoutput, th e pcm_in pin is input. in the pcm slave mode, the p cm_out pin is output, the pcm_in, pcm_fsc and pcm_clk pins are ou tput. W681307 publication release date: may, 2007 revision 1.3 - 58 - 10.3.3 status of speech interface when reset when the device is reset then the speech interface i/o pins will all be set as inputs and the associat ed interrupts will be masked. resetting the device will cause the speech interface pins (pc m[0:5] to be (general purpose) i/o ports. 10.4 internal codec control the speech interface block provides two control bit s to the internal codec. the bits are used for txmu te and dishpf. the signals are output from the speech interface block and go to th e internal codec. the values output by the speech i nterface on the two ports equates to the value programmed in dishpf and txmute, the b its are reset to 0. 10.5 pcm interface registers this section describes the speech interface registe r. 10.5.1 speech control 0 address access mode value at reset nominal value 0x1460 r/w 0x03 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 blocked (for test modes) fsync advance fsync 16/8bit fsync long/short blocked (for test modes) slave mode reserved pcmh1_dis according to the configuration of pcmh1_dis bit, th e pcm highway function and gpio function can be ser ved at four pcm pins at the same time. on the other hand, four pcm pins can jus t act for only pure pcm highway function or gpio fu nction. b0: pcmh1_dis =1 pcm i/o ports are gpio function. =0 pcm i/o ports are serial-parallel converter fun ction. b2: slave mode =1 effective pcm highway function wi ll operate at slave mode. =0 effective pcm highway function will operate at master mode. b5: fsync-16/8bit b4:fsync long/short x 0 short frame sync signal is selected. the period of fsync signal occupies 1 bit clock. 0 1 long frame sync signal is selected. and the per iod of fsync signal occupies 8 bits. 1 1 long frame sync signal is selected. and the per iod of fsync signal occupies 16 bits. b6: fsync advance =1 the pcm_fsc signal is transmit ted in advance of the pcm_clk by one system clock. =0 the pcm_fsc signal is transmitted at the rising edge of the pcm_clk 10.5.2 specific register address access mode value at reset nominal value 0x1461 r/w 0x00 W681307 publication release date: may, 2007 revision 1.3 - 59 - bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved reserved reserved blocked (for test modes) blocked (for test modes) 10.5.3 speech io direction address access mode value at reset nominal value 0x1462 r/w 0x0f bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved speechiod[3] speechiod[2] speechiod[1] speechiod[0] when set pcm interface as general i/o, this registe r set the i/o direction. speechiod[0] =1: pcm0 pin will be operated as input port. =0: pcm0 pin operated as output mode. speechiod[1] =1: pcm1 pin will be operated as input port. =0: pcm1 pin operated as output mode. speechiod[2] =1: pcm2 pin will be operated as input port. =0: pcm2 pin operated as output mode. speechiod[3] =1: pcm3 pin will be operated as input port. =0: pcm3 pin operated as output mode. 10.5.4 speech io input data address access mode value at reset nominal value 0x1463 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved speechioi[3] speechioi[2] speechioi[1] speechioi[0] speechioi when pcm interface is configured as inpu t port, this register reflects the input data. 10.5.5 speech io output data address access mode value at reset nominal value 0x1464 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved speechioo[3] speechioo[2] speechioo[1] speechioo[0] speechioo when pcm interface is configured as outp ut port, this register set to output data. W681307 publication release date: may, 2007 revision 1.3 - 60 - 10.5.6 speech io mask address access mode value at reset nominal value 0x1465 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved speechiom[3] speechiom[2] speechiom[1] speechiom[0] speechiom[3:0] when pcm interface configured as input port, this r egister mask the interrupt when pcm interface input port is interrupted. 10.5.7 fsync counter address access mode value at reset nominal value 0x1466 r 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved fsync-counter fsync-counter provide the status of the frame sync counter within the speech interface. 10.6 the multiplexer to connect 5 pcm channels to 4 proc essor channels 10.6.1 multiplexer control register address access mode value at reset nominal value 0x1467 r/w 0x11 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved pcm channel4 pcm channel3 pcm channel2 pcm channel1 pcm channel0 the function of the multiplexer is to choose 4 chan nels among the 5 pcm channels to be effective which can be connected to 4 processor channels by setting the multiplexer control registe r 0x1467. and the four processor channels labeled b y from c0 to c3 will connect to the effective pcm channels in numerical order of the ch annel label.the pcm channel4 (b4) have two input so urce: usb iso input and external pcm device. it is controlled by usb_en bit . setting usb_en =1, the usb iso data pass to pcm c hannel 4 . W681307 publication release date: may, 2007 revision 1.3 - 61 - 10.7 pcm highway interface 10.7.1 the introduction of pcm modes 10.7.1.1 master / slaver mode for master mode, pcm_clk and pcm_fsc is output port . for slaver mode, pcm_clk and pcm_fsc is input port. pcm_clk pcm_in pcm_out ............. ............. bitclk bitclk rx_delay1 ..... ..... tx_delay1 ..... ..... m l 8/16 bits m l 8/16 bits rx_delay2 ..... ..... tx_delay2 ..... ..... m l 8/16 bits m l 8/16 bits rx_delay3 ..... ..... tx_delay3 ..... ..... m l 8/16 bits m l 8/16 bits rx_delay4 ..... ..... tx_delay4 ..... ..... m l 8/16 bits m l 8/16 bits pcm_fsc 10.7.1.2 master mode in master mode, pcm_clk and pcm_fsc is output port. pcm_fsc 8k short sync or long sync. pcm_clk 1536 khz pcm_in when sync is coming, it starts to catch msb in (first sync rising + delay1 bits). lsb is depend ing 8bits or 16bits for first slot. data rate is 1x or 1/2 clk. pcm_out when sync is coming, it starts to send msb in (first sync rising + delay1 bits). lsb is depend ing 8bits or 16bits for first slot. data rate is 1x or 1/2 clk. pcm_fsc long sync mode pcm_clk (output) master mode with data rate = 1x clk pcm_fsc short sync mode pcm_in pcm_out hi-z hi-z msb msb lsb lsb (output) (output) W681307 publication release date: may, 2007 revision 1.3 - 62 - pcm_fsc long sync mode (output) master mode with data rate = 1/2 clk pcm_fsc short sync mode pcm_in pcm_out hi-z hi-z msb msb lsb lsb (output) (output) pcm_clk 10.7.1.3 slave mode in slave mode, pcm_clk and pcm_fsc is input port. pcm_fsc 8k short sync or long sync. pcm_clk 768 khz ~ 2048 khz pcm_in when sync is coming, it starts to catch msb in (first sync rising + delay1 bits). lsb is depend ing 8bits or 16bits for first slot. data rate is 1x or 1/2 clk. pcm_out when sync is coming, it starts to send msb in (first sync rising + delay1 bits). lsb is depend ing 8bits or 16bits for first slot. data rate is 1x or 1/2 clk. pcm_fsc long sync mode slave mode with data rate = 1x clk pcm_fsc short sync mode pcm_in pcm_out hi-z hi-z msb msb lsb lsb pcm_clk (input) (input) (input) pcm_fsc long sync mode slave mode with data rate = 1/2 clk pcm_fsc short sync mode pcm_in pcm_out hi-z hi-z msb msb lsb lsb (intput) (input) pcm_clk (intput) W681307 publication release date: may, 2007 revision 1.3 - 63 - 10.7.2 the description of pcm highway interface registers 10.7.2.1 pcm channel format and delay control of 1 st group (pcm b1, pcm b2) address access mode value at reset 0x1700h r/w 0x02 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pcmb1_dis half rate pcmb2_dis reserved hizen half/full reserved data 16/8bits reserved data 16/8bits set the bit to receive/transmit 16 bi ts; reset the bit to receive/transmit 8 bits. hizen half/full set the bit to tristate in the end of the bit. reset the bit to tristate in the fallin g edge of the end of the bit. pcmb2_dis =1: disabling the b2 channel of the pcm h ighway. =0: enabling the b2 channel of the pcm highway. half rate set the bit for one bit per 2 bitclk (dur ing data length being 16 bits=>0x1700 [1] =1?b1). r eset the bit for one bit per 1 bitclk. pcmb1_dis =1: disabling the b1 channel of the pcm h ighway. =0: enabling the b1 channel of the pcm highway. 10.7.2.2 tx delay1 address access mode value at reset 0x1701h r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tx delay1 set the values for delaying the transmitted bits of pcm b1 channel after the rising edge of the frame pulse. the resolution is one bitclk in full date rate and two bitclk in half data rate. 10.7.2.3 tx delay2 address access mode value at reset 0x1702h r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tx delay2 set the values for delaying the transmitted bits of pcm b2 channel after the tail bit of pcm b1 channe l. the resolution is one pcm bitclk in full date rate and two bitclk in half dat a rate. W681307 publication release date: may, 2007 revision 1.3 - 64 - 10.7.2.4 rx delay1 address access mode value at reset 0x1703h r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rx delay1 set the values for delaying the received bits of pc m b1 channel after the rising edge of the fsync. th e resolution is one bitclk in full date rate and two bitclk in half data rate. 10.7.2.5 rx delay2 address access mode value at reset 0x1704h r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rx delay2 set the values for delaying the received bits of pc m b2 channel after the tail bit of rx pcm highway b 1 channel. the resolution is one bitclk in full date rate and two bitclk in half dat a rate. 10.7.2.6 pcm channel format and delay control of 2nd group ( pcm b3, pcm b4) address access mode value at reset 0x1708h r/w 0x02 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pcmb3_dis half rate pcmb4_dis reserved hizen half/full reserved data 16/8bits reserved data 16/8bits set the bit to receive/transmit 16 bi ts; reset the bit to receive/transmit 8 bits. hizen half/full set the bit to tristate in the end of the bit. reset the bit to tristate in the fallin g edge of the end of the bit. pcmb4_dis =1: disabling the b4 channel of the pcm h ighway. =0: enabling the b4 channel of the pcm highway. half rate set the bit for one bit per 2 bitclk (dur ing data length being 16 bits=>0x1708 [1] =1?b1). r eset the bit for one bit per 1 bitclk. pcmb3_dis =1: disabling the b3 channel of the pcm h ighway. =0: enabling the b3 channel of the pcm highway. W681307 publication release date: may, 2007 revision 1.3 - 65 - 10.7.2.7 tx delay3 address access mode value at reset 0x1709h r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tx delay3 set the values for delaying the transmitted bits of pcm highway b3 channel after the tail bit of tx pc m highway b2 channel. the resolution is one bitclk in full date rate and two bitclk in half data rate. 10.7.2.8 tx delay4 address access mode value at reset 0x170ah r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tx delay4 set the values for delaying the transmitted bits of pcm highway b4 channel after the tail bit of tx pc m highway b3 channel. the resolution is one bitclk in full date rate and two bitclk in half data rate. 10.7.2.9 rx delay3 address access mode value at reset 0x170bh r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rx delay3 set the values for delaying the received bits of pc m highway b3 channel after the tail bit of rx pcm h ighway b2 channel. the resolution is one bitclk in full date rate and two bitclk in half data rate. 10.7.2.10 rx delay4 address access mode value at reset 0x170ch r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rx delay4 set the values for delaying the received bits of pc m highway b4 channel after the tail bit of rx pcm h ighway b3 channel. the resolution is one bitclk in full date rate and two bitclk in half data rate. W681307 publication release date: may, 2007 revision 1.3 - 66 - codec half aec #146eh #146fh #146ch #146dh #146ah #146bh # 1468h # 1469h multiplexer gain stage c0 c1 c2 c3 10.8 digital gain multiplexer there are 4 fine-tune on-chip gain stage allocated between multiplexer interface and half acoustic can celler block or behind multiplexer interface. this gain stage is implemented by a digi tal multiplexer to provide a range of +12 db to ?12 db with a resolution of 0.5 db per step. figure 10-3 is shown the location of this dig ital gain multiplexer. the 4 channels ft gain stage support gain adjustmen t for linear pcm signal for each pcm channel. each channe l has its independent gain registers for gain setti ng. figure 10-3 the location of digital fine-tuning g ain stage 10.8.1 fine-tuning gain stage registers 10.8.1.1 ftingain3 address access mode value at reset nominal value 0x1468 r/w 0x00 W681307 publication release date: may, 2007 revision 1.3 - 67 - bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved ftingain[5] ftingain[4] ftingain[3] ftingain[2] ftingain[1] ftingain[0] refer to table 10-1 for fine tune input gain. this gain is applied to the input data of processor chan nel c3. 10.8.1.2 ftoutgain3 address access mode value at reset nominal value 0x1469 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved ftoutgain[5] ftoutgain[4] ftioutgain[3] ftoutgain[2] ftoutgain[1] ftoutgain[0] refer to table 10-1 for fine tune output gain. this gain is applied to the output data of processor ch annel c3. 10.8.1.3 ftingain2 address access mode value at reset nominal value 0x146a r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved ftingain[5] ftingain[4] ftingain[3] ftingain[2] ftingain[1] ftingain[0] refer to table 10-1 for fine tune input gain. this gain is applied to the input data of processor chan nel c2. 10.8.1.4 ftoutgain2 address access mode value at reset nominal value 0x146b r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved ftoutgain[5] ftoutgain[4] ftioutgain[3] ftoutgain[2] ftoutgain[1] ftoutgain[0] refer to table 10-1 for fine tune output gain. this gain is applied to the output data of processor ch annel c2. 10.8.1.5 ftingain1 address access mode value at reset nominal value 0x146c r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved ftingain[5] ftingain[4] ftingain[3] ftingain[2] ftingain[1] ftingain[0] refer to table 10-1 for fine tune input gain. this gain is applied to the input data of processor chan nel c1. W681307 publication release date: may, 2007 revision 1.3 - 68 - 10.8.1.6 ftoutgain1 address access mode value at reset nominal value 0x146d r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved ftoutgain[5] ftoutgain[4] ftioutgain[3] ftoutgain[2] ftoutgain[1] ftoutgain[0] refer to table 10-1 for fine tune output gain. this gain is applied to the output data of processor ch annel c1. 10.8.1.7 ftingain0 address access mode value at reset nominal value 0x146e r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved ftingain[5] ftingain[4] ftingain[3] ftingain[2] ftingain[1] ftingain[0] refer to table 10-1 for fine tune input gain. this gain is applied to codec pcm output data. this gain can be also adjusted to consider the power requirement of the half acoustic echo can celler. 10.8.1.8 ftoutgain0 address access mode value at reset nominal value 0x146f r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved ftoutgain[5] ftoutgain[4] ftioutgain[3] ftoutgain[2] ftoutgain[1] ftoutgain[0] refer to table 10-1 for fine tune output gain. this gain is applied to codec pcm input data. this gain can be also adjusted to consider the power requirement of the half acoustic echo can celler. W681307 publication release date: may, 2007 revision 1.3 - 69 - table 10-1 fine-tuning input, output gain (decimal index). th e 5-bit numbers allow +/- 12 db adjustment in 0.5 d b steps and hard mute. ft in/out gain [4:0] gain value ft in/out gain [4:0 ] gain value 0x00 0 db 0x19 -0.5 db 0x01 0.5 db 0x1a -1.0 db 0x02 1.0 db 0x1b -1.5 db 0x03 1.5 db 0x1c -2.0 db 0x04 2.0 db 0x1d -2.5 db 0x05 2.5 db 0x1e -3.0 db 0x06 3.0 db 0x1f -3.5 db 0x07 3.5 db 0x20 -4.0 db 0x08 4.0 db 0x21 -4.5 db 0x09 4.5 db 0x22 -5.0 db 0x0a 5.0 db 0x23 -5.5 db 0x0b 5.5 db 0x24 -6.0 db 0x0c 6.0 db 0x25 -6.5 db 0x0d 6.5 db 0x26 -7.0 db 0x0e 7.0 db 0x27 -7.5 db 0x0f 7.5 db 0x28 -8.0 db 0x10 8.0 db 0x29 -8.5 db 0x11 8.5 db 0x2a -9.0 db 0x12 9.0 db 0x2b -9.5 db 0x13 9.5 db 0x2c -10.0 db 0x14 10.0 db 0x2d -10.5 db 0x15 10.5 db 0x2e -11.0 db 0x16 11.0 db 0x2f -11.5 db 0x17 11.5 db 0x30 -12.0 db 0x18 12.0 db 0x3f mute W681307 publication release date: may, 2007 revision 1.3 - 70 - 11. processor interface 11.1 overview the processor interface controls reads and writes m ade by the processor to the on-chip ram and on-chip registers. 11.2 functionality figure 11-1 shows the processor interface block dia gram. figure 11-1 illustration of the processor interfa ce 11.3 processor access sequencer the processor access sequencer has 2 functions ? internal register access sequencing ? on-chip ram access sequencing external ram accesses, external rom accesses and in ternal register reads are performed directly by the 8032turbo, the address decoder and read multiplexer. no action is required by the processor access sequencer. the operation of the processor access sequencer for internal register writes is shown in figure 11-2. note that ? the sequence of a register write is not affected by the setting of strech. ? the internal register clock enable signal sysclock2 en is active for 4 cycles to allow internal events to be scheduled after a W681307 publication release date: may, 2007 revision 1.3 - 71 - register writes. ? the internal address bus intaddress is a latched ve rsion of the processor address bus, updated when an internal accesses is required. this reduces internal transitions on the chip to save power. ! "!! # $ % figure 11-2 timing of internal register writes W681307 publication release date: may, 2007 revision 1.3 - 72 - the operation of the processor access sequencer for access to the on-chip ram is shown in figure 11-3. note that ? the on-chip ram is a clocked-synchronous ram. ? the data read out of the on-chip ram is latched in the processor interface. figure 11-3 timing of on-chip ram access W681307 publication release date: may, 2007 revision 1.3 - 73 - 11.4 read multiplexer the read multiplexer multiplexes the following data onto the internal 8032turbo data bus: ? on-chip registers ? on-chip ram ? speech processor registers ? off-chip bus interface each function performs local address decoding for b oth reads and writes. for register reads, each bloc k multiplexes the addressed register onto a single output bus and asserts a dat a valid signal. all internal modules present zero on the read data buses when not selected. in the case of support logic, processor interface, speech interface and interface logic these modules decode a lower part of the address bus, so may present data out at various points in the me mory map. for other blocks all the decoding is done within th e processor interface. a data inputs are qualified with appropriate addres s decoder outputs. this ensures that only the requi red sub-module data is presented to the 8032turbo. 11.5 processor interface control registers 11.5.1 auxopport address access mode value at reset nominal value 0x1470 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved cs1r2 cs1r1 cs1r0 auxop port1en auxopport1 auxop port0en auxopport0 cs1 and cs2 can be set as general output port, 0x14 70 bit1 and bit3 enable this function independently . auxopport0 means cs1 and auxopport1 means cs2. when you enable the general o utput function, the cs1/cs2 will be not in address decode mode. figure 11-4 shows /cs1 & /cs2 output multiplexer. auxopport0 the auxopport data bits contai n true data. auxopport0en when set, enable the auxopport 0. auxopport1 the auxopport data bits contai n true data. auxopport1en when set, enable the auxopport 1. the auxopport enables are active high. W681307 publication release date: may, 2007 revision 1.3 - 74 - 1 11 1 0 00 0 3 33 3 1 11 1 a uxo pp ort0 a uxo pp ort0 a uxo pp ort0 a uxo pp ort0 0x1470 [0] 0x1470 [0] 0x1470 [0] 0x1470 [0] a uxo pp ort0e n a uxo pp ort0e n a uxo pp ort0e n a uxo pp ort0e n 0 x1470[1 ] 0 x1470[1 ] 0 x1470[1 ] 0 x1470[1 ] /c s 1 /c s 1 /c s 1 /c s 1 2 22 2 0 00 0 /c s 1 /c s 1 /c s 1 /c s 1 /r d /r d /r d /r d /w r /w r /w r /w r 1 11 1 0 00 0 3 33 3 1 11 1 a uxo pp ort1 a uxo pp ort1 a uxo pp ort1 a uxo pp ort1 0x1470 [2] 0x1470 [2] 0x1470 [2] 0x1470 [2] a uxo pp ort1e n a uxo pp ort1e n a uxo pp ort1e n a uxo pp ort1e n 0 x1470[3 ] 0 x1470[3 ] 0 x1470[3 ] 0 x1470[3 ] /c s 2 /c s 2 /c s 2 /c s 2 2 22 2 0 00 0 /c s 2 /c s 2 /c s 2 /c s 2 /r d /r d /r d /r d /w r /w r /w r /w r 0x1 472[1:0 ] 0x1 472[1:0 ] 0x1 472[1:0 ] 0x1 472[1:0 ] 0x1 472[3:2 ] 0x1 472[3:2 ] 0x1 472[3:2 ] 0x1 472[3:2 ] p in n a m e p in n a m e p in n a m e p in n a m e p in n a m e p in n a m e p in n a m e p in n a m e figure 11-4 /cs1 & /cs2 output mu ltiplexer the cs1 range is defined as: cs1r2 cs1r1 cs1r0 depth address range 0 0 0 4kb 0x8000 0x8fff 0 0 1 8kb 0x8000 0x9fff 0 1 0 12kb 0x8000 0xafff 0 1 1 16kb 0x8000 0xbfff 1 0 0 20kb 0x8000 0xcfff 1 0 1 24kb 0x8000 0xdfff 1 1 0 28kb 0x8000 0xefff 1 1 1 32kb 0x8000 0xffff 11.5.2 diagsel address access mode value at reset nominal value 0x1471 r/w 0x00 W681307 publication release date: may, 2007 revision 1.3 - 75 - bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved reserved reserved reserved reserved 11.5.3 diag_cs address access mode value at reset nominal value 0x1472 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved cs2r2 cs2r1 cs2r0 cs2_sel[1] cs2_sel[0] cs1_sel[1] cs1_sel[0] cs1 & cs2 can be selected output for setting the bi ts cs1 & cs2 output multiplexer (see figure 11-4) cs1[1:0] / cs2[3:2] output 00 cs1 / cs2 01 cs1|rd / cs2|rd 10 cs1|wd / cs2 |wd 11 ~((cs 1 | rd) & (cs1 | wr)) / ~((cs 2 | rd) & (cs2 | wr)) the cs2 range is defined as: cs2r2 cs2r1 cs2r0 depth address range 0 0 0 4kb 0xf000 0xffff 0 0 1 8kb 0xe000 0xffff 0 1 0 12kb 0xd000 0xffff 0 1 1 16kb 0xc000 0xffff 1 0 0 20kb 0xb000 0xffff 1 0 1 24kb 0xa000 0xffff 1 1 0 28kb 0x9000 0xffff 1 1 1 32kb 0x8000 0xffff cs1 and cs2 can address 32 k totally. so for exampl e, you set cs2 for addressing 12 kb, then cs1 only address 20kb . cs1: 0x8000h~ 0xcfffh ; cs2 : 0xd0000h~0xffffh. W681307 publication release date: may, 2007 revision 1.3 - 76 - /cs3 31 20 / rd / wr 0x 1473[3:2] /cs3 pin name 11.5.4 diag_cs3 address access mode value at reset nominal value 0x1473 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved rd_wr_blk cs2_wait _en cs3_sel[1] cs3_sel[0] pwr_save[1] pwr_save[0] figure 11-5 cs3 output multiplexer cs3 output multiplexer is shown in figure 11-5. address mapping range of cs3 is 0x2000~0x5fff cs3_sel[1:0] output 00 cs3 01 cs3 | rd 10 cs3 | wd 11 ~((cs 3 | rd) & (cs3 | wr)) cs2_wait_en this is a wait state enable bit for cs2 controlled device. when set this bit, the wr/rd duration to cs2 controlled device will last from 4 clock cyc les to 8 clock cycles. rd_wr_blk when set this bit, the ext ernal rd/wr signal will not active (blocked) when a ccess internal ram/register (0x0000 to 0x1fff and 0x6000 to 0x7fff ), the default is not blocked. pwr_save [1:0] you can set pwr_save [1:0] to control ad/addr bus output state for i/o power s ave purpose. pwr_save[1:0] ad/addr bus 00 no power save feature. 01 ad/addr bus only active when t8032 rd/wr in the mask rom mode. 10 ad/addr bus only active when t8032 rd/wr external d evice (0x8000~0xffff),in the mask rom mode. 11 ad/addr bus always inactive. W681307 publication release date: may, 2007 revision 1.3 - 77 - 11.5.5 multiplier_enable address access mode value at reset nominal value 0x1474 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved reserved reserved reserved mul8x8_en mul8x8_en this is an enable bit of a fast 8x8 multiplier in t8032.when set this bit, a fast t8032 internal 8x8 multiplier will be active otherwise the original t8032 add-shift multi plier is the default choice. 11.6 in system programming mode in system programming mode is designed for fast pro gram on board flash. flash type includes 29, 39 and 49 series. the chip is provided two isp entry modes. one is hardware setting and th e other is software command mode. this function comes with the pc software, which tra nsfer the binary code to internal t8032 to program the external rom flash. isp function use internal t8032 uart or usb port to tra nsfer data, the default baud rate of the uart port is 9600bps, which can be set by remote pc program. there are four baud-rates for se lection, 9600bps, 19200bps, 28800bps and 57600bps. the double-speed mcu chip (2x), you can select optional 115200bps for flash p rogram. 11.6.1 hardware setting usage in the initial power-up state, the /cs2 pin will re placed as isp function hardware setting pin. when / cs2 pin set to low and re-power up the system, the chip will execute the internal isp code, and wait for pc command and binary data to up date the external rom flash. if the /cs2 is set to output purpose pin (the pin is defau lt pull-up), this chip will in normal mode. the fla sh needed an external write signal. the isp_wr pin of the chip needs to connect to the /wr pin of the external flash and which pin only active in isp operation. 11.6.2 software command usage this isp function can provide the system program update fro m the internal usb or uart ports with software comm and and don?t need any hardware modification. therefore the baseband chip doesn?t need extra circuit to su pport this function. figure 11-6 is shown the function description and s pecification. W681307 publication release date: may, 2007 revision 1.3 - 78 - program set isp_en isp_en isp_en isp_en isp_en isp_rst isp_rst isp_rst isp_rst rst hw_isp_en hw_isp_en hw_isp_en hw_isp_en rst baseband internal mask rom isp code operation to baseband internal mask rom isp code operation to baseband internal mask rom isp code operation to baseband internal mask rom isp code operation to download program code to external flash from usb or download program code to external flash from usb or download program code to external flash from usb or download program code to external flash from usb or uart port dependent on the isp command source uart port dependent on the isp command source uart port dependent on the isp command source uart port dependent on the isp command source baseband external flash baseband external flash baseband external flash baseband external flash rom code operation rom code operation rom code operation rom code operation mcu mcu mcu mcu into into into into idle idle idle idle mode mode mode mode hardware switch to run the hardware switch to run the hardware switch to run the hardware switch to run the internal mask isp rom code of internal mask isp rom code of internal mask isp rom code of internal mask isp rom code of baseband. and the all the baseband. and the all the baseband. and the all the baseband. and the all the internal registers of baseband internal registers of baseband internal registers of baseband internal registers of baseband chip will band-switch to p1.7. chip will band-switch to p1.7. chip will band-switch to p1.7. chip will band-switch to p1.7. isp program completes the isp mode mcu mcu mcu mcu into into into into idle idle idle idle mode mode mode mode baseband baseband baseband baseband external flash external flash external flash external flash rom code rom code rom code rom code operation operation operation operation hardware switch to normal hardware switch to normal hardware switch to normal hardware switch to normal operation to run the external operation to run the external operation to run the external operation to run the external flash rom code. flash rom code. flash rom code. flash rom code. isp hardware module generates isp hardware module generates figure 11-6 the software isp operation procedure 11.6.3 isp_ctrl (hardware & watchdog reset control registe r) address access mode value at reset nominal value 0x1900 rw 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 isp_en reserved reserved reserved reserved reserved usb_isp uart_isp this isp control register is provided the in-system -programming function to update the system program code without modification hardware. this function can be enabled by the bit 7 of isp_ctrl control register. and the enable comma nd which is come from the internal uart port or usb interface. uart_isp this bit is reserved for isp mask ro m program recognition which type isp mode is enable d. when isp enabled command is come from internal uart port. then the normal pr ogram will set this bit for recognition in isp mode period before enabled isp_en bit. and download program data will come from uart port in the isp programming period. usb_isp the bit function is the same as u art_isp. isp_en when set this bit will enable is p mode to program the external flash rom via the in ternal usb interface or uart port. 11.6.4 specific register address access mode value at reset nominal value 0x1901 rw 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 blocked (for test modes) reserved reserved reserved reserved reserved reserved reserved W681307 publication release date: may, 2007 revision 1.3 - 79 - 11.7 mask rom mode mask rom mode is designed to use the internal mask rom, besides this mcu chip also can disable the int ernal mask rom to use external flash rom. although mcu chip provide isp m ode and mask rom mode but you cannot use it simulta neously. each function is independent function. 11.7.1 usage when set ext_rom pin to low, the chip will execute the internal mask rom code. when set ext_rom pin to high, the chip will execute the external flash rom code. W681307 publication release date: may, 2007 revision 1.3 - 80 - 12. speech processor the speech processor provides a complete implementa tion, including ? 4 duplex channels ? 1 channel echo canceller ? a mixer block ? programmable tone generators the speech processor supports a-law, -law and 16-b its linear pcm formats. echo canceller channels sup port 16 bits linear pcm only. the speech processor is implemented by an optimized micro-coded dsp, an external fir filter engine and one digital gain multiplexer . the architecture of the speech processor can be sho wn in figure 12-1. the microcode dsp core: ? performs tone generation ? performs pcm mixing the fir engine: ? performs real-time echo estimation ? implements network echo suppression ? calculates the echo cancellation filter coefficient s ? performs intermediate calculations on the echo esti mation error 12.1 transcoder dsp the transcoder dsp is a low power implementation an d has the following features: ? low power consumption and low gate count ? group delay under 14 s / channel ? dtmf and call progress tones ? sidetone generation and volume control ? requires only 4.1 mips per channel the transcoder dsp supports a-law, -law and 16-bit s linear pcm formats. format selection is programma ble on a by-channel basis. the signal flow (per channel) is shown in figure 12 -1 below pcm format mixer matrix mixer matrix output gain input gain + + tone gen + side tone pcm_in pcm_out figure 12-1 transcoder signal flow there are dual-tone generators for each pcm channel . these can generate dtmf and common signaling tone s, as well as user notification tones. the tones may be added in eithe r direction. a mixer function is enabled by setting 1401[0]. four full-duplex pcm W681307 publication release date: may, 2007 revision 1.3 - 81 - channels can be connected / mixed together in any c ombination. this function is controlled by programm able registers. moreover, the speech logic interface (which is not needed by the codec) of four channels must be enabled. 12.2 the description of the activation registers 12.2.1 mixer_en address access mode value at reset nominal value 0x1401 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 blocked (for test modes) blocked (for test modes) blocked (for test modes) blocked (for test modes) blocked (for test modes) blocked (for test modes) blocked (for test modes) mixer_en mixer_en set to enable the mixer block. 12.2.2 speech logic_en address access mode value at reset nominal value 0x1420 r/w 0x04 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 blocked (for test modes) blocked (for test modes) blocked (for test modes) blocked (for test modes) blocked (for test modes) blocked (for test modes) blocked (for test modes) speech logic_en speech logic_en set to enable speech logic i nterface (which is not needed by the codec) of four channels. 12.3 the description of transcoder dsp registers the transcoder block is programmed via microprocess or accessible programming registers. all registers allow read/write access and reset to zero except as noted. all bits not specified below are reserved or blocked and should only be written with zeros. unspecified bits read b ack zero. the transcoder registers are divided into `global r egisters' and `channel-specific registers'. global registers ? consist of sidetone (0x148d) and lookback_en (0x148 e) registers. channel-specific registers channel-specific registers appear in four groups at offsets of sixteen bytes. ? channel 0 registers appear at addresses 0x1480 -> 0 x148c ? channel 1 registers appear at addresses 0x1490 -> 0 x149c ? channel 2 registers appear at addresses 0x14a0 -> 0 x14ac ? channel 3 registers appear at addresses 0x14b0 -> 0 x14bc W681307 publication release date: may, 2007 revision 1.3 - 82 - 12.3.1 connect0 address access mode value at reset nominal value 0x1480 r/w 0x01 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pcm channel 3 pcm channel 2 pcm channel 1 pcm channel 0 blocked (for test modes) blocked (for test modes) blocked (for test modes) * blocked (for test modes) specify mixing among four pcm channels. this regist er enables the connections of each pcm channels. bits [7:4] correspond to pcm ch annels 3:0. * blocked (for test modes) must be set to 1 . when the value of the bit is set to 1, it enables t he addition of the corresponding channel in mixing. an additive connection is set up between the specified channels. 12.3.2 specified register address access mode value at reset nominal value 0x1481 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved reserved reserved blocked (for test modes) blocked (for test modes) 12.3.3 specified register address access mode value at reset nominal value 0x1482 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved reserved reserved reserved blocked (for test modes) 12.3.4 specified register address access mode value at reset nominal value 0x1483 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved reserved reserved reserved blocked (for test modes) W681307 publication release date: may, 2007 revision 1.3 - 83 - 12.3.5 pcmmode0 address access mode value at reset nominal value 0x1484 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved reserved reserved comp_format pcm_linear pcm_linear =1, pcm port 0 operates in 16-bit lin ear mode. =0, 8-bit compressed pcm. comp_format if pcm port 0 is in compressed mode, =1, a-law, =0, -law 12.3.6 inputgain0 address access mode value at reset nominal value 0x1485 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved inputgain[3] inputgain[2] inputgain[1] inputgain[0] inputgain[3:0] pcm input gain table is listed as be low table 12-1. this gain is applied directly to th e pcm input value. 12.3.7 outputgain0 address access mode value at reset nominal value 0x1486 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved outputgain[3] outputgain[2] outputgain[1] outputgain[0] outputgain[3:0] pcm output gain table is listed as below table 12-2. this gain is applied after the mi xer matrix and tone generation. 12.3.8 tonefreqa0 address access mode value at reset nominal value 0x1488 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tonefreqa frequency of tone a = tonefreqa * 15.625 (hz) W681307 publication release date: may, 2007 revision 1.3 - 84 - 12.3.9 tonefreqb0 address access mode value at reset nominal value 0x1489 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tonefreqb frequency of tone b = tonefreqb * 15.625 (hz) 12.3.10 tonevola0 address access mode value at reset nominal value 0x148a r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved tonevola[4] tonevola[3] tonevola[2] tonevola[1] tonevola[0] tone level is listed as below table 12-3 for tone g enerator a. 12.3.11 tonevolb0 address access mode value at reset nominal value 0x148b r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved tonevolb[4] tonevolb[3] tonevolb[2] tonevolb[1] tonevolb[0] tone level is listed as below table 12-3 for tone g enerator b. 12.3.12 toneena0 address access mode value at reset nominal value 0x148c r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved reserved reserved tx_tone rcv_tone rcv_tone =1, add tone generators to the receiving ( pcm_out) path. receive tones are added just before the pcm output gain stage. tx_tone =1, add tone generators to the transmitting (pcm_in) path. transmit tones are added just after the pcm input gain stage. warning: enabling tones in both directions at the s ame time causes the output frequencies to double. W681307 publication release date: may, 2007 revision 1.3 - 85 - 12.3.13 sidetone address access mode value at reset nominal value 0x148d r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved sidetone[4] sidetone[3] sidetone[2] sidetone[1] sidetone[0] sidetone[4:0] side tone gain is listed as below tab le 12-4. this is applied to all active pcm channels between the mixer matrix and pcm formatting. please refer to 0x14af to enable the active sideton e channel. sidetone[4:0] =0, to disable side tone. 12.3.14 loopback_en address access mode value at reset nominal value 0x148e r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 * blocked (for test modes) reserved reserved reserved blocked (for test modes) blocked (for test modes) blocked (for test modes) loopback_en loopback_en =1, loopback behind the side tone funct ion in the transmitting (pcm_in) path. * blocked (for test modes) must be set to 1. 12.3.15 specified register address access mode value at reset nominal value 0x148f r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 blocked (for test modes) 12.3.16 connect1 ~ toneena1 address access mode value at reset nominal value 0x1490 ~ 0x149c r/w 0x00 the functions are the same as channel 0. 12.3.17 connect2 ~ toneena2 address access mode value at reset nominal value 0x14a0 ~ 0x14ac r/w 0x00 the functions are the same as channel 0. W681307 publication release date: may, 2007 revision 1.3 - 86 - 12.3.18 sidetonechannel_ena address access mode value at reset nominal value 0x14af r/w 0x01 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved sidetone_ch3 sidetone_ch2 sidetone_ch1 sidetone_ch0 the register can enable side tone individually for the each active pcm channel. 12.3.19 connect3 ~ toneena3 address access mode value at reset nominal value 0x14b0 ~ 0x14bc r/w 0x00 the functions are the same as channel 0. 12.4 pcm mixer matrix the registers connect0-3 specify channels which sho uld be connected together and enable the correspond ing pcm channels. the connection registers of each specified pcm channels can be set to the same value simultaneously. the r esult is the same that one of each registers be set. for example, the pcm0 and pcm1 ch annels need to be connected. so the 1480 and 1490 c an be set to 31. the effect is the same that only 1480 or 1490 is set. 12.5 gain tables there are four gain functions in this block: pcm i/ o gain, side tone gain and tone gain (level). table 12-1 the pcm input gain is provided to allo w minor corrections for board-level analogue gain p roblems. the 4-bit numbers allow +/- 10 db adjustments and hard mute. inputgain (3:0) nominal gain actual g ain 0x00 0 db 0 db 0x01 +1 db +1.0 0x02 +2 db +2.0 0x03 +3 db +2.8 0x04 +4 db +4.2 0x05 +6 db +6.0 0x06 +8 db +8.0 0x07 +10 db +9.5 0x08 - (hard mute) - 0x09 -10 db -10.1 0x0a -8 db -8.5 0x0b -6 db -6.0 0x0c -4 db -4.1 0x0d -3 db -3.2 0x0e -2 db -1.8 0x0f -1 db -1.2 W681307 publication release date: may, 2007 revision 1.3 - 87 - table 12-2 the pcm output gain is provided to all ow minor corrections for board-level analogue gain problems. the 4-bit numbers allow +/- 16 db adjustments and hard mute. outputgain(3:0) nominal gain actual gai n 0x00 0 db 0 db 0x01 +1.5 db +1.9 0x02 +3 db +3.5 0x03 +5 db +4.9 0x04 +7 db +7.0 0x05 +10 db +9.9 0x06 +13 db +13.5 0x07 +16 db +15.6 0x08 - (hard mute) - 0x09 -16 db -18.1 0x0a -13 db -12.0 0x0b -10 db -8.5 0x0c -7 db -6.0 0x0d -5 db -4.1 0x0e -3 db -2.5 0x0f -1.5 db -1.2 table 12-3 tone levels are specified in linear va lues, referenced to ? of the max pcm level (+3.17 d bm0). tone level = -2.85 dbm0 + 20 log10 (tonevol / 32). because there are 32 legal values, the following table contains only example values. tone generator gain value tonevolx(4:0) actual level (dbm0) tonevolx(4:0) actual level (dbm0) tonevolx(4:0) actual level (dbm0) 0x00 disable 0x0b -12.1251 0x16 -6.1045 0x01 -32.9530 0x0c -11.3694 0x17 -5.7184 0x02 -26.9324 0x0d -10.6741 0x18 -5.3488 0x03 -23.4106 0x0e -10.0304 0x19 -4.9942 0x04 -20.9118 0x0f -9.4312 0x1a -4.6535 0x05 -18.9736 0x10 -8.8706 0x1b -4.3257 0x06 -17.3900 0x11 -8.3440 0x1c -4.0098 0x07 -16.0510 0x12 -7.8475 0x1d -3.7050 0x08 -14.8912 0x13 -7.3779 0x1e -3.4106 0x09 -13.8681 0x14 -6.9324 0x1f -3.1258 0x0a -12.9530 0x15 -6.5086 W681307 publication release date: may, 2007 revision 1.3 - 88 - table 12-4 the side tone gain is adjustable from -32 db to 0 db in 1 db steps. setting this register to 0 disables side tone. side tone gain value index value index value 0x00 mute 0x10 -15 db 0x01 0 db 0x11 -16 db 0x02 -1 db 0x12 -17 db 0x03 -2 db 0x13 -18 db 0x04 -3 db 0x14 -19 db 0x05 -4 db 0x15 -20 db 0x06 -5 db 0x16 -21 db 0x07 -6 db 0x17 -22 db 0x08 -7 db 0x18 -23 db 0x09 -8 db 0x19 -24 db 0x0a -9 db 0x1a -25 db 0x0b -10 db 0x1b -26 db 0x0c -11 db 0x1c -28 db 0x0d -12 db 0x1d -30 db 0x0e -13 db 0x1e -32 db 0x0f -14 db 0x1f -36 db W681307 publication release date: may, 2007 revision 1.3 - 89 - 13. echo canceller 13.1 half aec block diagram the acoustics echo cancellation unit removes the ec ho signal inserted by the speaker and space. figure 13-1 illustrates the block diagram of the ha lf acoustics echo canceller in the speech processor . figure 13-1 the signal flow through the acoustics echo canceller in the speech processor 13.1.1 acoustics suppression when enabled (and so, switched into the network out put data path) the acoustic suppression unit will i nsert a configurable attenuation factor into the network output path. the attenuatio n will switch between a maximum and minimum value d epending on the presence or absence of speech on the network output data path. when speech is present the attenuation will conver ge towards the minimum value. when speech is absent the attenuation will converge towards the maximum value. the attenuation factor will not switch abruptly between these two factors but will exponentially converge f rom one to the other. when enabled the network output data path will incl ude the following arithmetic unit n attenuatio as nout nout _ ? W681307 publication release date: may, 2007 revision 1.3 - 90 - 13.1.2 network power estimation to detect the double talk condition an estimate of the long term network power is required. the long term network power is estimated with the f ollowing arithmetic unit ( ) ( ) ( ) ? ? ? ?? ? ? ? ? ?? ? ? + ? ? ? + ? ? ? ? ? 17 _ _ _ _ 16 _ _ _ _ 1 16 _ _ _ _ 1 2 _ _ _ 2 2 tc attack network long vd tc attack network long vd n tc attack network long vd n n n threshold network long vd pnin nin pnin pnin the short term network power is estimated with the following arithmetic unit ( ) ( ) ? ?? ? ? ?? ? ? ? ? + ? ? ? ? 16 _ _ _ _ 1 16 _ _ _ _ 1 2 2 tc attack network short vd n tc attack network short vd n n n pninshort nin pninshort pninshort the deviation term network power is estimated with the following arithmetic unit n n n pninshort power network off cut pnin pnindev ? ? _ _ _ 13.1.3 acoustic power estimation this speech will have originated at the near end an d does not correspond to a reflected echo signal. s peech is deemed to occur if the long term acoustic power exceeds a predetermined thresho ld or if the short term acoustic power exhibits sud den variations. if speech is being carried over both the network and acoustic interfac es then the double talk condition occurs. the long term acoustic power is estimated with the following arithmetic unit ( ) ( ) ? ?? ? ? ?? ? ? ? ? + ? ? ? ? 16 _ _ _ _ 1 16 _ _ _ _ 1 2 2 tc attack acoustic long dt n tc attack acoustic long dt n n n pain ain pain pain the short term acoustic power is estimated with the following arithmetic unit ( ) ( ) ? ?? ? ? ?? ? ? ? ? + ? ? ? ? 16 _ _ _ _ 1 16 _ _ _ _ 1 2 2 tc attack acoustic short dt n tc attack acoustic short dt n n n painshort ain painshort painshort W681307 publication release date: may, 2007 revision 1.3 - 91 - 13.1.4 auto gain control the short term cancelled power is estimated with th e following arithmetic unit ( ) ( ) ? ?? ? ? ?? ? ? ? ? + ? ? ? ? 16 _ _ _ 1 16 _ _ _ 1 2 2 tc attack st agc n tc attack st agc n n pgshort hsout pgshort pgshort the agc module is operated with the following algor ithm if ( ) pgshort hsout > then hsout pgshort = if threshold noise agc pgshort _ _ < then 1 = sg else pgshort threshold agc sg _ = if sg max agc sg _ _ > then sg max agc sg _ _ = the long term agc module gain is estimated with the following arithmetic unit ( ) ( ) ? ?? ? ? ?? ? ? ? ? + ? ? ? ? 16 _ _ _ 1 16 _ _ _ 1 2 2 tc attack lg agc n tc attack lg agc n n sglong sg sglong sglong if sg sglong > then sg sglong = 13.2 the software interface of speech processor the following registers are used to configure the e cho canceller. all registers may be both read and w ritten by software. the width of each location will be a byte within the memory map. some locations may have unused bits which will be returned undefined values on a read cycle. information in these bit positions will be discarded on write cycles. the registers within the echo cancellation unit may be segmented into two classes activation registers and performance adjustment registers. an overview of each register class and n ominal values to program each register is presented . 13.3 activation registers 13.3.1 up_config address access mode value at reset nominal value 0x14c0 r/w 0x00 0x82 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 agc reserved blocked (for test modes) blocked (for test modes) blocked (for test modes) blocked (for test modes) as1_ena blocked (for test modes) W681307 publication release date: may, 2007 revision 1.3 - 92 - as1_ena when set, the acoustic suppression (as1) fu nction will be enabled. agc when set, enable agc function. * the acoustic suppression (as2) function is always enabled. 13.3.2 up_reset address access mode value at reset nominal value 0x14c1 r/w 0x08 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 blocked (for test modes) reserved reserved aec_reset power down blocked (for test modes) blocked (for test modes) blocked (for test modes) power down when set, power down the aec unit to sav e power. speech signal will bypass aec module. aec_reset when set, setting this bit will cause the aec registers, including the activation registers and performance adjustment registers, to be reseted to their hardware reset values. 13.3.3 ec_belta address access mode value at reset nominal value 0x14c2 r/w 0x03 0xe0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ns_enable netacidle * blocked (for test modes) absolute blocked (for test modes) absolute when set, the double talk detection algorithm is based on absolute value of acoustic po wer. netacidle when set, the double sides don?t have any voice; it will mute in network side. ns_enable if this bit is set "0" , noise suppressor is by-passed. if this bit is set "1", then noise suppressor is enabled. * blocked (for test modes) must be set to 1. 13.3.4 specific register address access mode value at reset nominal value 0x14c3 r/w 0x03 0x03 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved blocked (for test modes) 13.4 performance adjustment registers 13.4.1 acoustic suppressor register 13.4.1.1 as_build_up_time address access mode value at reset nominal value 0x14c4 r/w 0x07 0x55 W681307 publication release date: may, 2007 revision 1.3 - 93 - bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 as2_build_up_time as1_build_up_time control register for acoustic suppression factor co nvergence towards target. raising (lowering) the value of this field will low er (raise) the inertial delay present when the acou stic suppression unit responds to the presence or absence of speech. 13.4.1.2 as_max_atten address access mode value at reset nominal value 0x14c5 - 0x14c6 r/w 0x1ca8 0x0200 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 c5 as1 & as2_max_atten bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 c6 as1 & as2_max_atten maximum attenuation value will be utilized by the a coustic suppression algorithm. the maximum value of this field provides an attenua tion factor of 1. the minimum value provides an attenuation factor of 0. 13.4.1.3 as_min_atten address access mode value at reset nominal value 0x14c7 - 0x14c8 r/w 0xffff 0xffff bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 c7 as1 & as2_min_atten bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 c8 as1 & as2_min_atten minimum attenuation value will be utilized by the a coustic suppression algorithm. the maximum value of this field provides an attenua tion factor of 1. the minimum value provides an attenuation factor of 0. 13.4.2 acoustic side control registers 13.4.2.1 dt_long_acoustic_attack_tc address access mode value at reset nominal value 0x14c9 r/w 0x09 0x09 W681307 publication release date: may, 2007 revision 1.3 - 94 - bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved dt_long_acoustic_attack_tc acoustic long term power estimation?s attacking tim e constant. this field defines the inertial delay utilized for the long term acoustic power estimation. raising th e value of this field reduces the inertia and will make the estimation more responsive whilst lowering the field will cause the power estimation algorithm to be less responsive to bursts of energy on the acoustic. 13.4.2.2 dt_short_acoustic_attack_tc address access mode value at reset nominal value 0x14ca r/w 0x0b 0x0b bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved dt_short_acoustic_attack_tc acoustic short term power estimation?s attacking ti me constant this field defines the inertial delay utilized for the short term acoustic power estimation. raising t he value of this field reduces the inertia and will make the estimation more responsive whilst lowering the field will cause the power estimation algorithm to be less responsive to bursts of energy on the acoustic side. 13.4.2.3 dt_acoustic_hangover_time address access mode value at reset nominal value 0x14cb - 0x14cc r/w 0x0020 0x0340 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 cb dt_acoustic_hangover_time bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cc dt_acoustic_hangover_time this field defines the inertial delay of the double talk detection algorithm for acoustic side. following the detection of the double talk conditio n there is a programmable inertial delay (in pcm sa mple periods 125us) following the disappearance of the double talk condition. for the duration of this delay period the double talk cond ition is assumed to remain. if double talk does not reappear during this window then the echo cancellation unit will revert back to acoustic training mode. 13.4.2.4 dt_ acoustic _dev_threshold address access mode value at reset nominal value 0x14cd - 0x14ce r/w 0x0666 0x0040 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 cd dt_ acoustic_dev_threshold W681307 publication release date: may, 2007 revision 1.3 - 95 - bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ce dt_ acoustic_dev_threshold this field defines the instantaneous acoustic power change that is deemed to correspond to speech and is used to detect short term changes in voice level on the acoustic interface.raising (lowering) this field will raise (lower) the change in acoustic power required for the detection of speech (and hence the double talk condition). 13.4.2.5 dt_short_acoustic_threshold address access mode value at reset nominal value 0x14cf - 0x14d0 r/w 0x0404 0x0040 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 cf dt_short_ acoustic_threshold bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 d0 dt_short_ acoustic_threshold this field defines the power threshold that is deem ed to correspond to speech. raising(lowering) this field will raise (lower) the acoustic power required for the detection of speech (and hen ce the double talk condition). 13.4.3 network side control registers 13.4.3.1 vd_long_network_attack_tc address access mode value at reset nominal value 0x14d1 r/w 0x09 0x09 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved vd_long_network_attack_tc network long term power estimation?s attacking time constant this field defines the inertial delay utilized for the long term network power estimation. raising the value of this field reduces the inertia and will make the estimation more responsive whilst lowering the field will cause the power estimation algorithm to be less responsive to bursts of energy on the network side. 13.4.3.2 vd_short_network_attack_tc address access mode value at reset nominal value 0x14d2 r/w 0x0b 0x0b bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved vd_short_network_attack_tc W681307 publication release date: may, 2007 revision 1.3 - 96 - network short term power estimation?s attacking tim e constant this field defines the inertial delay utilized for the short term network power estimation. raising th e value of this field reduces the inertia and will make the estimation more responsive whilst lowering the field will cause the power estimation algorithm to be less responsive to bursts of energy on the network side. 13.4.3.3 vd_network_hangover_time address access mode value at reset nominal value 0x14d3 - 0x14d4 r/w 0x0009 0x0340 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 d3 vd_network_hangover_time bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 d4 vd_network_hangover_time this field defines the inertial delay of the voice detection algorithm for the network side. following the detection of the speech on the networ k interface there is a programmable inertial delay (in pcm sample periods) following the disappearance of the speech signal. for the dur ation of this delay period the speech is assumed to remain. if speech does not reappear during this window then the echo cancellation unit will revert back to channel training mode. 13.4.3.4 vd_network_dev_threshold address access mode value at reset nominal value 0x14d5 - 0x14d6 r/w 0x0666 0x01b0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 d5 vd_network_dev_threshold bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 d6 vd_network_dev_threshold this field defines the instantaneous network power change that is deemed to correspond to speech and i s used to detect short term changes in voice level on the network interface. raising (lowering) this field will raise (lower) th e change in network power required for the detectio n of speech. W681307 publication release date: may, 2007 revision 1.3 - 97 - 13.4.3.5 vd_long_netwrok_threshold address access mode value at reset nominal value 0x14d7 - 0x14d8 r/w 0x0666 0x1050 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 d7 vd_long_network_threshold bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 d8 vd_long_network_threshold minimum power level constitutes speech over the net work interface, as measured by the long term power estimation algorithm. 13.4.3.6 vd_short_netwrok_threshold address access mode value at reset nominal value 0x14d9 - 0x14da r/w 0x040e 0x03c0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 d9 vd_short_network_threshold bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 da vd_short_network_threshold minimum power level constitutes speech over the net work interface, as measured by the short term power estimation algorithm. 13.4.3.7 vd_cut_off_network_power address access mode value at reset nominal value 0x14db - 0x14dc r/w 0x0666 0x08a0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 db vd_cut_off_network_power bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dc vd_cut_off_network_power configurable bias for network power estimation. thi s field defines the zero reference for the network power estimation algorithm. 13.4.3.8 specific register address access mode value at reset nominal value 0x14dd r/w 0x00 W681307 publication release date: may, 2007 revision 1.3 - 98 - bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved reserved reserved reserved blocked (for test modes) 13.4.4 acoustic / network active status address access mode value at reset nominal value 0x14de r 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved acousticactive networkactive blocked (for test modes) blocked (for test modes) blocked (for test modes) blocked (for test modes) acoustic active = 1, reflect the status of acous tic power network active = 1, reflect the status of netwo rk power. 13.4.5 agc control registers 13.4.5.1 agc_threshold address access mode value at reset nominal value 0x14df - 0x14e0 r/w 0x0800 0x1000 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 df agc_threshold bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 e0 agc_threshold the agc threshold is set the maximum output power f rom agc module. the purpose is set properly gain to prevent voice signal clipping. 13.4.5.2 agc_noise_threshold address access mode value at reset nominal value 0x14e1 - 0x14e2 r/w 0x00c8 0x0100 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 e1 agc_noise_threshold bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 e2 agc_noise_threshold the calculated input power with time constant agc_s t_attack_tc is less than the agc_noise_threshold, t hen agc gain is set to unit gain. it is assumed that the input powe r is background signal. W681307 publication release date: may, 2007 revision 1.3 - 99 - 13.4.5.3 agc_max_sg address access mode value at reset nominal value 0x14e3 r/w 0x02 0x0a bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved agc_max_sg the agc module has maximum gain to amplifier the ec ho cancelled input signal. 13.4.5.4 specific register address access mode value at reset nominal value 0x14e4 r/w 0x0f 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved *blocked for test modes *blocked for test modes. set the 4 bits to 1. 13.4.5.5 agc_lg_attack_tc address access mode value at reset nominal value 0x14e5 r/w 0x0b 0x33 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 agc_lg_attack_tc_pos agc_lg_attack_tc_neg agc_lg_attack_tc_neg the field defines the inertial delay utilized for the long term gain estimation when the agc gain is increasing. raising the value of this field reduces the inertial and will make the estimation more responsive while lowering the field will cause the gain estimation algorithm to be less responsive to bursts of gain on the agc. agc_lg_attack_tc_pos the field defines the inertial delay utilized for the long term gain estimation when the agc gain is decreasing. raising the value of this field reduces the inertial and will make the estimation more responsive while lowering the field will cause the gain estimation algorithm to be less responsive to bursts of gain on the agc. 13.4.5.6 agc_st_attack_tc address access mode value at reset nominal value 0x14e6 r/w 0x09 0x09 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved agc_st_attack_tc attack time for short term agc power estimation. th is field defines the inertial delay utilized for th e short term agc power estimation. raising the value of this field reduces the inertia l and will make the estimation more responsive whil e lowering the field will cause the power estimation algorithm to be less responsive to bursts of energy on the agc. W681307 publication release date: may, 2007 revision 1.3 - 100 - 13.4.6 noise suppressor registers 13.4.6.1 ns_sttack_tcand_gain address access mode value at reset nominal value 0x14e7 r/w 0x00 0xb5 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 shorttermnspowerattacktc[7:4] noise_suppressor_index[3:0] noise_suppressor_index this 4-bit field defines the gain of noise suppress or noise_suppressor_index[3:0] noise suppressor level (db) noise_suppressor_index[3:0] noise suppressor l evel (db) 0 -1 9 -10 1 -2 a -11 2 -3 b -12 3 -4 c -13 4 -5 d -14 5 -6 e -15 6 -7 f -16 7 -8 8 -9 shorttermnspowerattacktc the 4-bit field defines the "time constant" to calc ulate the power of voice that enters the noise supp ressor module. so "noise suppressor" can determine if current powe r of voice is larger than "noise threshold" or not. the operation is just like "short term acoustic pow er time constant. 13.4.6.2 ns_atten_dw_up_tc address access mode value at reset nominal value 0x14e8 r/w 0x00 0x55 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 noise_fall_tc[4:7] noise_rise_tc[0:3] noise_rise_tc this 4-bit field defin es the time constant of noise suppressor gain from the gain specified by "noise_suppressor_index" to "0db". larger value, faster speed . noise_fall_tc this 4-bit field defin es the time constant of noise suppressor gain from "0db" to the gain specified by "noise_suppressor_index". larger value, faster speed . 13.4.6.3 ns_active_power_msb address access mode value at reset nominal value 0x14e9 r/w 0x00 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ns_active_power_msb the most significant byte of noise threshold. W681307 publication release date: may, 2007 revision 1.3 - 101 - 13.4.6.4 ns_active_power_lsb address access mode value at reset nominal value 0x14ea r/w 0x00 0x40 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ns_active_power_lsb the most significant byte of noise threshold. so "noise_threshold" = {ns_active_power_msb,ns_acti ve_power_lsb} 13.4.7 aec soft clip in order to reduce clipping distortion, a soft clip ping function has been implemented in gtx1. a secon d gain (gtx1_sc) and an overload threshold point (th_sc) is programmable. gain gtx1 is changed to gtx1_sc if the input signal level of the gtx1 gain state is greater than th_sc. note that the input signal power level is estimated in the gtx1 gain stage using the follo wing arithmetic unit ( ) p p a gtx gtx gtx tc gtx gtx tc 1 1 1 16 1 1 16 1 2 2 = ? + ? ? _ _ if ( p gtx 1 th_sc) gtx factor gtx sc 1 1 _ _ ? else gtx factor gtx 1 1 _ ? gtx gtx gtx factor a a gtx avg gt tc avg gt tc rin gtx avg 1 1 2 1 1 2 1 16 16 1 ? ? + ? ? ? ( ) _ ( _ ) ( _ ) p gtx 1 gtx1 input power with time constant gtx1_tc gtx avg 1 gtx1 average gain with time constant gt_tc W681307 publication release date: may, 2007 revision 1.3 - 102 - max_ level gtx1*th_sc th_sc input _ signal output _ signal gtx1 gtx1_sc max_ level figure 13-2 block diagram of the soft clipping fu nction of gtx1 13.4.7.1 soft clip control address access mode value at reset nominal value 0x14eb r/w 0x00 0x03 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved reserved reserved dtsc_enable vdsc_enable soft_clip control register is used to enable the so ft clipping function. there are two bits in this re gister to control two soft clip blocks independently. vdsc_enable when set, enable soft clip function for network signal before network signal is sent to ae c module. when reset, disable soft clip function. so network signal is sent to aec module directly. dtsc_enable when set, enable soft clip function for acoustic signal after acoust ic signal is sent out from aec module. when reset, disable soft clip function. so acoustic signal is sent to next stage directly. W681307 publication release date: may, 2007 revision 1.3 - 103 - 13.4.7.2 vd soft clip normal index address access mode value at reset nominal value 0x14ec r/w 0x00 0x12 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved vdsc_normal_index[5:0] vdsc_normal_index[5:0] is used to control the gain of vd soft_clip module at normal mode. the gain sel ection range is the same as "digital gain multiplexer" and is reproduced below vdsc_normal_index[5:0] hex value gain vdsc_normal_index[5:0] hex value gain 0x00 0 db (default) 0x19 - 0.5 db 0x01 0.5 db 0x1a - 1.0 db 0x02 1.0 db 0x1b - 1.5 db 0x03 1.5 db 0x1c - 2.0 db 0x04 2.0 db 0x1d - 2.5 db 0x05 2.5 db 0x1e - 3.0 db 0x06 3.0 db 0x1f - 3.5 db 0x07 3.5 db 0x20 - 4.0 db 0x08 4.0 db 0x21 - 4.5 db 0x09 4.5 db 0x22 - 5.0 db 0x0a 5.0 db 0x23 - 5.5 db 0x0b 5.5 db 0x24 - 6.0 db 0x0c 6.0 db 0x25 - 6.5 db 0x0d 6.5 db 0x26 - 7.0 db 0x0e 7.0 db 0x27 - 7.5 db 0x0f 7.5 db 0x28 - 8.0 db 0x10 8.0 db 0x29 - 8.5 db 0x11 8.5 db 0x2a - 9.0 db 0x12 9.0 db 0x2b - 9.5 db 0x13 9.5 db 0x2c - 10.0 db 0x14 10.0 db 0x2d - 10.5 db 0x15 10.5 db 0x2e - 11.0 db 0x16 11.0 db 0x2f - 11.5 db 0x17 11.5 db 0x30 - 12.0 db 0x18 12.0 db 0x3f mute W681307 publication release date: may, 2007 revision 1.3 - 104 - 13.4.7.3 vd soft clip low index address access mode value at reset nominal value 0x14ed r/w 0x00 0x06 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved vdsc_low_index[5:0] vdsc_low_index[5:0] is used to control the gain of vd soft_clip module at low mode. the gain selection range is the same as "vd soft clip normal index". 13.4.7.4 vd soft clip threshold address access mode value at reset nominal value 0x14ee - 0x14ef r/w 0x0400 0x4000 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ee vdsc_threshold bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ef vdsc_threshold vdsc_threshold is used to determine the selection o f soft clip gain. when the input network power is l arger then vdsc_threshold, vdsc_low_index gain is used, otherwise vdsc_normal_ index gain is used. 13.4.7.5 shorttermprenetworkpowerattacktc address access mode value at reset nominal value 0x14f0 r/w 0x07 0x0b bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved shorttermprenetworkpowerattacktc[3:0] shorttermprenetworkpowerattacktc[3:0] is the time c onstant which is used to calculate the short term n etwork power for vd soft clip. 13.4.7.6 vdsc attack tc address access mode value at reset nominal value 0x14f1 r/w 0x07 0x05 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved vdsc_attacktc[3:0] when soft clip gain is switched between normal and low, an embedded smoothing function is used to smoo th the gain change. vdsc_attacktc[3:0] is a time constant to control th e smoothing speed. W681307 publication release date: may, 2007 revision 1.3 - 105 - 13.4.7.7 dt soft clip normal index address access mode value at reset nominal value 0x14f2 r/w 0x00 0x18 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved dtsc_normal_index[5:0] dtsc_normal_index[5:0] is used to control the gain of dt soft clip module at normal mode. the gain sel ection range is the same as "vdsc_normal_index". 13.4.7.8 dt soft clip low index address access mode value at reset nominal value 0x14f3 r/w 0x00 0x0c bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved dtsc_low_index[5:0] dtsc_low_index[5:0] is used to control the gain of dt soft_clip module at low mode. the gain selection range is the same as "vdsc_ normal_index". 13.4.7.9 dt soft clip threshold address access mode value at reset nominal value 0x14f4 - 0x14f5 r/w 0x0400 0x1140 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 f4 dtsc_threshold bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f5 dt_sc_threshold dtsc_threshold is used to determine the selection o f soft clip gain. when the output acoustic power is larger then dtsc_threshold, dtsc_low_index gain is used, otherwise dtsc_normal_ index gain is used. W681307 publication release date: may, 2007 revision 1.3 - 106 - 13.4.7.10 shorttermpostacousticpowerattacktc address access mode value at reset nominal value 0x14f6 r/w 0x07 0x0b bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved shorttermpostacousticpowerattacktc[3:0] shorttermpost acoustic powerattacktc[3:0] is the time constant which is us ed to calculate the short term acoustic power for dt soft clip. 13.4.7.11 dtsc attack tc address access mode value at reset nominal value 0x14f7 r/w 0x07 0x05 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved dtsc_attacktc[3:0] when soft clip gain is switched between normal and low, an embedded smoothing function is used to smoo th the gain change. dtsc_attacktc[3:0] is a time constant to control th e smoothing speed. 13.5 acoustic side / network side power measurement 13.5.1 acoustic_short_term_power address access mode value at reset nominal value 0x15c0- 0x15c1 r 0x0000 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 c0 acoustic_short_term_power bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 c1 acoustic__short_term_power short term acoustic power calculated by the double talk detector (dt). 13.5.2 acoustic_long_term_power address access mode value at reset nominal value 0x15c2- 0x15c3 r 0x0000 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 W681307 publication release date: may, 2007 revision 1.3 - 107 - c2 acoustic_long_term_power bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 c3 acoustic_long_term_power long term power on acoustic side estimated by the d ouble talk detector (dt). 13.5.3 acoustic_power_deviation address access mode value at reset nominal value 0x15c4- 0x15c5 r 0x0000 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 c4 acoustic_power_deviation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 c5 acoustic_power_deviation acoustic power deviation estimated by the double ta lk detector (dt). 13.5.4 acoustic / network active status address access mode value at reset nominal value 0x15c6 r 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved reserved reserved acousticactive networkactive bit[1] = 1, reflect the status of acoustic power. bit[0] = 1, reflect the status of network power. 13.5.5 network_short_term_power address access mode value at reset nominal value 0x15c8 - 0x15c9 r 0x0000 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 c8 network_short_term_power W681307 publication release date: may, 2007 revision 1.3 - 108 - bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 c9 network_short_term_power network short term power calculated by vd modules. 13.5.6 network_long_term_power address access mode value at reset nominal value 0x15ca- 0x15cb r 0x0000 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ca network_long_term_power bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cb network_long_term_power network long term power calculated by vd modules. 13.5.7 network_power_deviation address access mode value at reset nominal value 0x15cc- 0x15cd r 0x0000 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 cc network_power_deviation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cd network_power_deviation network power deviation estimated by the voice dete ctor (vd). 13.5.8 acoustic / network active status address access mode value at reset nominal value 0x15ce r 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved reserved reserved acousticactive networkactive bit[1] = 1, reflect the status of acoustic power. bit[0] = 1, reflect the status of network power. W681307 publication release date: may, 2007 revision 1.3 - 109 - 14. system function 14.1 power on reset the power on reset (por) block generates a internal reset signal to reset the whole chip after connect ing the power supply voltage the chip. the power on reset circuit responds to the vo ltage difference applied between avdd and agnd. fig ure 14-1 shows the power reset circuit. when avdd is rising slowly starting from zero to th e signal poweronresetn will be low until avdd passe d the power-on voltage level von. after a delay time (about 37ms for 13.824mhz c lock) reset_out goes high and the actual reset sequ ence starts. if avdd does not pass von voltage, then the poweronresetn stays low, causing the oscillator to run and having most of t he digital logic circuits being in an active reset mode. if avdd sinks below the power -off voltage level voff, poweronrestn will become l ow again. the hysteresis voltage between von and voff is need to overcome a ?reset oscillation? phenomenon that otherwise might occur if avdd decrease due to the activity during the reset sequence. figure 144-1 analog part of the power on reset fu nction. 14.1.1 codec on/off scheme address access mode value at reset 0x1500 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved periodselection codec on/off codeconoff scheme enable codeconoff_scheme_enable set ?1 ? to enable hardwired codec on/off scheme. set ?0? to use independent on/off control from 0x1509. codec on/off set?1? to turn on codec. set ?0? to turn off codec. periodselection set to select the duration length betwe en codec_digital_on/off and codec_analog_on/off. bit[3:2] period 2?b00 2 ms 2?b01 4 ms 2?b10 8 ms 2?b11 16 ms W681307 publication release date: may, 2007 revision 1.3 - 110 - 14.1.2 codec digital part address access mode value at reset nominal value 0x1501 r/w 0x80 90 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 abf_mode dac_dither_level[1:0] dac_dither _enable adc_abf_length[1:0] codec_fifo_ ptr_reset codec_fifo_ reset codec_fifo_reset when set, clear codec fifo content after each 8k operation. codec_fifo_ptr_reset when set, reset codec fifo pointer after each 8k operation. adc_abf_length[1:0] select the limit cycle length to do adaptive bit flipping (abf) alg orithm. abf_l[1:0] limit cycle length 0 4 1 6 2 8 3 10 dac_dither_enable when set, enab le the dither input in dac path dac_dither_level[1:0] select the dith er level in the dac path. da_dither_level[1:0] dither level 0 17 bit 1 15 bit 2 16 bit 3 18 bit abf_mode when set, select adaptive bit flipping algorithm (abf) mode i n the analog codec modulator. 14.2 adc adaptive bit flip probability address access mode value at reset nominal value 0x1502 r/w 0xff 80 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adc_abf_prob this byte set the adaptive bit flip probability of the adc path in the codec modulator. when set adc_a bf_prob to 0xff will disable the adaptive bit-flipping algorithm, and se t to 0x00 means always enable the adaptive bit-flip ping algorithm if the limit cycle length condition is detected. W681307 publication release date: may, 2007 revision 1.3 - 111 - 14.3 sounder signal selection address access mode value at reset nominal value 0x1503 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 blocked (for test modes) reserved rclk_sndr_se l refclksel refclkon pdmen sndrsigsel there are two sounders signal to be selected to con nect to sndr pin. this subsection describes the sou nder signal of pdm (pulse density modulation) format. the selection of different soun der signal and the related control bits are shown i n 0x1503[1:0]. pdmen when set, the tx path of codec will be hardwa re muted, the over sampled dtmf signal is switched to sounder signal path. so except to generate sounder signal, this bit should be reset to 0 while codec i s active. sndrsigsel when set, the sounder signal comes from the dtmf generator in the speech processor. the dtm f signal will be over sampled to 1 bit signal, which is call ed pulse density modulation (pdm) format. the pdm format signal then connects to pin sndr while pdmri ngen=1. the control registers of dtmf generator are allocated from addresses 1488h~148ch =0, the sounder signal comes from the ringer tone generator with pulse width modulation (pwm) format. the control registers of ringer tone generator are allocated from addresses 1447h~144ah refclkon when set, ena ble reference clock generation circuit. refclksel reference cl ock rate selection. refclksel[4:3] reference clk rate 0 13.824 mhz 1 6.912 mhz 2 3.456 mhz 3 1.728 mhz rclk_sndr_sel switch the function of pin sndr. set ?1? to configure the sndr pin as refclock output. set ?0? to configure the sndr pin as sndr output. W681307 publication release date: may, 2007 revision 1.3 - 112 - codec digital pcm format linear pcm codec analog half aec 0 1 1 0 tone geneator ringer tone generation (dd209_rt) 0x1485 0x1486 0x1488-0x148c 0x1484 0x14c1 codecapd 0x1509 [6] pdmen 0x 1503 [1] swc_in daout pdm pwm sndr sndrsigsel 0x 1503[0] adown figure 14-2 sounder signal selection circuit system clock rclk_sndr_sel 0 1 2 refclksel[1:0] 00 01 10 11 sndr_in 01 muxed_sndr counter to 7 negedge clk control logic control refclkon cnt on figure 14-3 reference clock frequency rate and fu nction selection circuit. 14.4 frequency adjustment of crystal oscillator a 13.824 mhz crystal is connected to pin xtal1 and xtal2. but the accuracy of the system clock will af fect the performance and power saving capability of a handset operating in s uspend mode. the frequency deviation resulted from the variation of crystal device and external load capacitances can be adjusted by the o n-chip capacitances. faco (frequency adjustment of crystal oscillator) c ontrols the connection of on-chip capacitance cg an d cd to the crystal oscillator pins xtal1 and xtal2 respectively. the total maximu m value is 11.9pf per pin. therefore this register can control the frequency of the crystal oscillator at 13.824 mhz. accurately. faco address access mode value at reset nominal value 0x1504 r/w 0x00 W681307 publication release date: may, 2007 revision 1.3 - 113 - bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 faco faco[bit 7] when set, add an 8 pf to cg and cd each . faco[bit 6] when set, add an 4 pf to cg and cd each . faco[bit 5] when set, add an 2 pf to cg and cd each . faco[bit 4] when set, add an 1 pf to cg and cd each . faco[bit 3] when set, add an 0.5 pf to cg and cd ea ch. faco[bit 2] when set, add an 0.25 pf to cg and cd e ach. faco[bit 1] when set, add an 0.125 pf to cg and cd each. faco[bit 0] when set, add an 0.0625 pf to cg and cd each. 14.5 specific register address access mode value at reset nominal value 0x1505 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved blocked (for test modes) blocked (for test modes) blocked (for test modes) blocked (for test modes) 14.6 vag selection address access mode value at reset nominal value 0x1506 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vc_vag [2:0] reserved reserved reserved reserved reserved vag default voltage is 1.5v. and the vag level can be programmed by software with following table. vc_vag [2:0] bin hex vag (v) default 000 0 1.50 001 1 1.57 010 2 1.67 011 3 1.80 100 4 2.00 101 5 2.33 110 6 1.50 111 7 1.50 W681307 publication release date: may, 2007 revision 1.3 - 114 - 14.7 tg gain register address access mode value at reset nominal value 0x1507 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved tg_a gain[2] tg_a gain[1] tg_a gain[0] reserved tg_b gain[2] tg_b gain[1] tg_b gain[0] tg op amp of the codec is implemented as a two ampl ifiers cascade to provide the necessary gain for lo w signal microphone input. the first stage (tg_a) is designed as a full differenti al high impendence and low noise amplifier. this am plifier gain can be set as bypass or maximum gain 18db for microphone input. the second stage (tg_b) is also full differential amplifier an d provides maximum gain 24db for the application requirement. it is according th is register to set different gain in the codec, equ ivalent architecture is shown in figure 14-4. the tg amplifier gain table is listed as belo w tg_a gain[2:0] tg_b gain[2:0] bin hex gain [db] bin hex gain [db] 0000 0 0 db 0000 0 0 db 0001 1 6 db 0001 1 6 db 0010 2 12 db 0010 2 12 db 0011 3 18 db 0011 3 18 db 0100 4 bypass 0100 4 24 db 0101 5 bypass 0101 5 24 db 0110 6 bypass 0110 6 24 db 0111 7 bypass 0111 7 24 db tg+ tg- 15k 15k 1st tg 15k 15k ,30k , 60k, 120k ti1+ ti2+ 15k ti1- ti2- 0 1 01 mux 0x1521[0] 15k ,30k , 60k, 120k ti1- ti2- 15k 15k 0x1521[0] , 0x1507[6] 15k 15k 15k ti1+ ti2+ 15k 2nd tg 15k ,30k , 60k, 120k, 240k 15k ,30k , 60k, 120k, 240k figure 14-4 equivalent schematics for tg op amp. W681307 publication release date: may, 2007 revision 1.3 - 115 - 14.8 po gain register address access mode value at reset nominal value 0x1508 r/w 0x88 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 po2_pd po2gain [2] po2gain [1] po2gain [0] po1_pd po1gain [2] po1gain [1] po1gain [0] the gains of po1 and po2 op amp are set according t o this register value. the maximum driving capabili ty of po1 is 120 and po2 is 16 . the po1 and po2 can be power down by the correspo nding control bits of po gain register. note that the po op amps can be also power down by the codec_ctrl register (0x1509). the po amplifier gain table is listed as below. po1 gain [3:0] po2 gain [7:4] bin hex gain [db] bin hex gain [db] 0000 0 0 db 0000 0 0 db 0001 1 2 db 0001 1 2 db 0010 2 4 db 0010 2 4 db 0011 3 6 db 0011 3 6 db 0100 4 8 db 0100 4 8 db 0101 5 10 db 0101 5 10 db 0110 6 -2 db 0110 6 -2 db 0111 7 -4 db 0111 7 -4 db 1xxx disable 1xxx disable W681307 publication release date: may, 2007 revision 1.3 - 116 - the equivalent resistance is shown in figure 14-5. po1+ r po 1- 15k r 15k unit gain ro po 1 po 2 po2+ po2- 15k 15k po2_pd 0x1508 b[7] po1_pd 0x1508 b[3] figure 14-5 equivalent schematics for po op amp W681307 publication release date: may, 2007 revision 1.3 - 117 - 14.9 the pcm codec 14.9.1 block diagram figure 14-6 shows the block diagram of the speech c odec-filter. figure 14-6 the block diagram of the pcm codec-fi lter 14.9.2 analog interface and signal path the built in linear 14-bit pcm codec-filter uses ? technology. there are two paths in the block, a tr ansmit path and a receive path. 14.9.2.1 transmit path in ? codec-filter an analog signal input, from a microphone interface , is passed to three terminal operational amplifier s (ti+, ti-, tg) driving a typical 2 k load externally to amplify the input analog signal . the modulator block over samples the analog signa l at 1.536 mhz with one bit resolution. the next anti-aliasing decimation filte r reduces the sampling frequency from 1.536 mhz (1 bit) to 32 khz (15 bit). digital bi- quad filters perform the decimation from 32k to 8 k hz and ccitt low-pass filtering at 3400 hz. the dig ital hpf block performs the high-pass filtering at 300 hz. in the final step, t he 14 bit a/d conversed data is sent by the transmi t path to the dsp engine for further signal processing. 14.9.2.2 receive path in ? codec-filter a 14-bit linear digital signal from the dsp engine is first passed to the digital anti-aliasing interp olation filter block. the interpolation block performs the reverse operation of the decimat ion filter (described above in the transmit path) a nd the sampling rate will be increased from 8 khz (14 bits) to 1.536 mhz (14 bits). the di gital demodulator will then reduce the 14-bit sampl es (1.024 mhz) to 1 bit (1.536 mhz). the digital output signal will be passed to a 3400 hz switched capacitor low-pass filter with si n(x)/x correction and an analog smoothing filter to reduce the spectral components of the switched capacitor filter. finally, the anal og output signal is sent to the unit gain power amplifier ro, which is capable of driving a 2 k load connected to the vag pin. the last stage of the received path is a pair of po wer driver po1- (po2-) and po1+ (po2+) which is con nected in a push-pull (differential) configuration. the po driver can accommodate large gain ranges by adjusting two external resistors for applications such as driving a handset receiver (or a speaker). this differential circuit is capable of driving a 120 (16 ) load. W681307 publication release date: may, 2007 revision 1.3 - 118 - 14.9.3 control register: codec_ctrl the functional description and read/write status of each bit are illustrated in this section. the read or write status of each bit is indicated by the symbol r or w described in table 14-1. symbol type meaning r/w read/write data may be read or written by micro -processor. table 14-1: read/write status description in contro l register address access mode value at reset nominal value 0x1509 r/w 0xc0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 codec digdis codecapd reserved reserved analog loopback reserved reserved reserved codecdigdis [bit7]: =1, disable the codec digital p art, =0, enable the codec digital part. codecapd [bit6]: =1, to disabled the codec analog p art to save power. especially when using the pdm mode sounder signal, only the codec digital filter is necessary. =0, codec analog part enabled. analog loopback [bit 3]: =1, setting this bit causes an analog loopback from the receive path to the transmit path. internally the ro output in the receive path is rou ted to the transmit gain control in the transmit path; the op-amp tg is bypassed. this feat ure is useful for self-testing to neglect the external connecting circuit, shown in figure 14 -7. . figure 14-7 the signal flow of analog lookback W681307 publication release date: may, 2007 revision 1.3 - 119 - 14.9.4 specific register address access mode value at reset nominal value 0x150a r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 blocked (for test modes) 14.9.5 specific register address access mode value at reset nominal value 0x150b r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 blocked (for test modes) reserved reserved reserved blocked (for test modes) blocked (for test modes) blocked (for test modes) blocked (for test modes) 14.10 receive_diag address access mode value at reset nominal value 0x150c r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved p3.5_a1 _sel p3.4_a0 _sel cs3_enable p1.4_waitstate_sel p1.5_sel p1.6_sel[1] p1.6_sel[0] b[1:0] p1.6_sel[1:0]= 0, pin 44= p1.6 port 1 bit 6 of embedded t8032. 1, pin 44= x undefined. signal. 2, pin 44= x undefined. signal. 3, pin 44= p1.6 port 1 bit 6 of embedded t8032. b[2] p1.5_sel= 0 pin 45= p1.5 or /cs3 port 1 bit 5 of embedded t8032 or external chip select. 1 pin 45= x undefined. signal b[3] p1.4_waitstate_sel= 0, pin 46= p1.4 port 1 bit 4 of embedded t8032. 1, pin 46= wait state input the input pin with pull-hi gh can receive wait signal from external device. b[4] cs3_enable= 0 pin 45= p1.5 port 1 bit 5 of emb edded t8032. 1 pin 45= /cs3 external chip select. b[5] p3.4_a0_sel= 0, pin37= p3.4 port 3 bit 4 of embedded t8032. 1, pin37= a0 a0 address of embedded t8032. b[6] p3.5_a1_sel= 0, pin36= p3.5 port 3 bit 5 of embedded t8032. 1, pin36= a1 a1 address of embedded t8032. if kr is used as gpio function besides setting spi _enable 0x1720 [7] = 0 (disable spi), 0x150c [7] mu st be set ?0?. W681307 publication release date: may, 2007 revision 1.3 - 120 - p3.4 01 a0 p3.4_a0_sel 150c[5] sim_clk uart_en & sim_en 1554[7-6] p3.4/ a0/ rxd1/sim_clk p3.5 01 a1 p3.5_a1_sel 150c[6] 01 uart_txd1 uart_en 1554[7] p3.5/ a1/ txd1 00 10 01 11 uart_rxd1 x p1.6_ sel [1:0] ( 0x150c [1: 0 ] ) 2 10 p1.5 p1.6 p1.5_ sel [b2] ( 0x150c [b2] ) 10 0 spi_ enb 0 spi_ enb mosi ( spi master output ; slave input) 1 sdi (df_spi) p 1.5/ mosi / sdi 1 01 sdo (df_spi) df_ enb p1.6/miso / sdo miso ( spi master input ; slave output ) x x x cs3_enable [b4] ( 0x150c [b4] ) 10 /cs3 3 p1.6 /cs3 / the usages of pin44 and pin45 are illustrated in fi gure 14-8. figure 14-8 the multiplexers of pin44 and pin45 the usages of pin36 and pin37 are illustrated in fi gure 14-9. figure 14-9 the multiplexers of pin36 and pin37 W681307 publication release date: may, 2007 revision 1.3 - 121 - 14.11 specific register address access mode value at reset nominal value 0x150d r/w 0x19 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved blocked (for test modes) blocked (for test modes) blocked (for test modes) blocked (for test modes) blocked (for test modes) blocked (for test modes) 14.12 enallclock address access mode value at reset nominal value 0x150e r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 speedup32k reserved reserved reserved dump mask rom 8032 clk output selection read mask rom enable enallclock enallclock when set, most of the clocks will be ena bled. read mask rom enable when set, enable read_access f or mask rom 8032 clk output selection when set, p1.4 will outpu t system clock used by on chip tb8032. if chip is c onfigured as double system clock speed, it output the x2 system clock. dump mask rom when set, enable mask rom test mode. speedup32k when set, 32k clock will replace with 13 .824 system clock for speed up testing. 14.13 codec_test_sel address access mode value at reset nominal value 0x150f r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 codec_test _sel[7] codec_test _sel[6] codec_test _sel[5] codec_test _sel[4] codec_test _sel[3] codec_test _sel[2] codec_test _sel[1] codec_test _sel[0] codec_test-sel[3:0] =0001, loopback da output. =0010, loopback ad output. =0011, assign da output to ?0?. =0100, loopback da input. =0101, test alu function. =0110, set value to internal register d2. =0111, calculate checksum of code rom. =1000, calculate checksum of coefficient rom. =1001, route external input (pdr) to ad input. =1010, output code rom content. =1011, output coefficient rom content. codec_test-sel[7:4] =0001, 1-bit ad input. =0010, adc fifo pointer. =0011, adc 1 st -stage sinc filter output. =0100, adc 2 nd ?stage sinc filter output. =0101, adc lpf output. =0110, adc hpf output. =0111, adc output. =1000, dac input. =1001, dac 1 st ?stage sinc filter output. =1010, dac lpf output W681307 publication release date: may, 2007 revision 1.3 - 122 - =1011, dac 2 nd ?stage sinc filter output. =1100, 1-bit da output. =1101, dac fifo pointer. 14.14 test_sysclkout address access mode value at reset nominal value 0x1510 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved reserved reserved test_sysclko ut blocked (for test modes) test_sysclkout when set, the sysclkout signal switches to pin res et_out. 14.15 bgp_lpf_en address access mode value at reset nominal value 0x1511 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bgp_lpf_en blocked (for test modes) blocked (for test modes) blocked (for test modes) blocked (for test modes) blocked (for test modes) bgp_lpf_en when set, the switch is o pen and bandgap low pass filter is enabled. when reset, the switch is close and bandgap low pas s filter is disabled. bandgap bandgap bandgap bandgap generator generator generator generator bgap reset: sw close reset: sw close reset: sw close reset: sw close set: sw open set: sw open set: sw open set: sw open supply power: vbat supply power: vbat supply power: vbat supply power: vbat 500k ohm bgp_lpf_en 14.16 codec status indicator address access mode value at reset nominal value 0x1512 r 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved adc_fifo _overflow adc_fifo _underflow dac_fifo _overflow dac_fifo _underflow adc_sinc _overflow adc_sinc _underflow W681307 publication release date: may, 2007 revision 1.3 - 123 - adc_fifo_overflowfifo pointer overflow in the adc p ath. adc_fifo_underflowfifo pointer underflow in the adc path. dac_fifo_overflowfifo pointer overflow in the dac p ath. dac_fifo_underflowfifo pointer underflow in the dac path. adc_sinc_overflowoverflow indication for adc sinc f ilter. adc_sinc_underflowunderflow indication for adc sinc filter. 14.17 bandgap voltage adjustment address access mode value at reset nominal value 0x1513 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved vbgp_trimming[5:0] bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 80mv 40mv 20mv 10mv 5mv bandgap voltage is default 1v. you can fine tune ba ndgap voltage follow below formula. when set vbgp_trimming[5] = 1, bandgap voltage = 1v 5mv * vbgp_trimming[4:0] when set vbgp_trimming[5] = 0, bandgap voltage = 1v 5mv * vbgp_trimming[4:0] where vbgp_trimming [4:0] is a decimal value and ranges from 0 to 31 14.18 specific register address access mode value at reset nominal value 0x1514 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 blocked (for test modes) blocked (for test modes) blocked (for test modes) blocked (for test modes) 14.19 linear regulator voltage controller register address access mode value at reset nominal value 0x1515 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved reg_lv[1] reg_lv[0] reserved reserved the output voltage of the embedded linear regulator (reg) is correlated to the internal bandgap voltag e. any tolerance and deviation of the bandgap voltage will cause a deviation of the o utput voltage of the embedded linear regulator. in order to ease the usage, the adjustment possibilities of output voltage of the l inear regulator have been built in to compensate th e bandgap variation in process. reg_lv[1:0] reg_lv [1:0] reg output voltage 00 3.0v 01 3.1v 10 3.2v 11 3.3v W681307 publication release date: may, 2007 revision 1.3 - 124 - 14.20 core pwr_det address access mode value at reset nominal value 0x1518 r 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved cpwr_det reserved reserved blocked (for test modes) blocked (for test modes) cpwr_det this bit is for core power volta ge monitor purpose and read only. when the core pow er voltage is below 1.7v, this bit will set to low. if the core power voltage is above 1.8v, this bit will set to high. normally, the cor e power voltage is 1.9v. this core power voltage monitor function can generate the interrupt and locate at 0x144d[5] regi ster. 14.21 da high pass filter selection address access mode value at reset nominal value 0x151a r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 disable hpf da_dither_select reserved reserved reserved reserved reserved reserved disable hpf when set, disable the high pass filter d to a directory da_ditehr_select when set, change d to a dither fun ction is add level (no sign) W681307 publication release date: may, 2007 revision 1.3 - 125 - 14.22 ti path selection there is a multiplexer at the input stage to choose which the receiving signal comes from address access mode value at reset nominal value 0x1521 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved ti2ntopo2 ti2ntopo1 reserved ti2_buffer_sel blocked (for test modes) path_sel path_sel when set, the signal is come from ti1- a nd ti1+ terminal to internal tg op amp when reset, the signal is come from ti2- and ti2 + terminal to internal tg op amp ti2_buffer_sel when set this bit, the ti2 inp ut will provide high input impedance to meet applic ation requirement. ti2ntopo1 when set, the signal ti2n will be conne cted to internal po1 amp. when reset, the signal ti2n will be disconnected to internal po1 amp. ti2ntopo2 when set, the signal ti2n will be conne cted to internal po2 amp. when reset, the signal ti2n will be disconnected to internal po2 amp. the multiplexers of the ti path selection are shown in figure 14-10. W681307 publication release date: may, 2007 revision 1.3 - 126 - figure 14-10 the multiplexers of the ti path sele ction W681307 publication release date: may, 2007 revision 1.3 - 127 - 15. serial peripheral interface 15.1 serial peripheral interface ? spi signals ? sck: input pin in slave mode; output pin in master mode. serial clock from master. max clock rate is t bd mhz (depends on how fast the cpu to read a word of rece ived data). ? /spi_cs: input pin in slave mode; output pin in mas ter mode. low active chip select signal from master . ? miso: output pin in slave mode; input pin in master mode. slave data out to the input of master. ? mosi: input pin in slave mode; output pin in master mode. master data out to the input of slave. if the phase of the clock is zero, i.e. cpha = 0, d ata is latched at the rising edge of the clock with cpol = 0, and at the falling edge of the clock with cpol = 1. if cpha = 1, the polaritie s are reversed. cpol = 0 means falling edge, cpol = 1 rising edge. the transmission clock edges are the reversed of sampli ng edges, shown in figure 15-1. timing diagram of c pha = 0 and cpha = 1 is shown in figure 15-2 and figure 15-3. figure 15-1 sampling edges of different modes figure 15-2 timing diagram of cpha = 0 ( ss is the pin /spi_cs) W681307 publication release date: may, 2007 revision 1.3 - 128 - figure 15-3 timing diagram of cpha = 1 ( ss is the pin /spi_cs) 15.1.1 spi_control 0 address access mode value at reset nominal value 0x1720 r/w 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 spi_enable spi_master_mo de reserved reserved dumpcomp reserved cpha cpol spi_enable spi interface enable. i f spi_enb=0, the spi is disabled and pins defined a s original functions. default to 0. spi_master_mode set to 1 in master mode. def ault to slave mode cpol clock polarity, if cp ol=0, clock is active high; if cpol=1, clock is act ive low. default to 0. cpha clock phase, determine d the sampling clock edge of sclk. default to 0. dumbcomp when this bit is on and the received byte is the same as dumpbyte (0x1724), th en no write to rx fifo. spi mode 0 = 0x80; spi mode 1 = 0x82; spi mode 2 = 0x81; spi mode 3 = 0x83; note: 0x1720[1:0] = ?10? is mode 1 in figure 1; 0x1 720[1:0] = ?01? is mode 2 in figure 1. 15.1.2 spi_control 1 address access mode value at reset nominal value 0x1721 r/w 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 spi_clock reserved reserved rxdepth_intr[3:0] spi_clock set master spi clock spee d. (master mode only) 00 1.152mhz 01 576khz 10 256khz 11 64khz the spi in slave mode support maximum clock speed i s 576k. rxdepth_intr an rxint interrupt event 1723[ bit 4] is generated when received byte count reache s rxdepth_intr[bit 3:0] +1 bytes. W681307 publication release date: may, 2007 revision 1.3 - 129 - 15.1.3 spi status address access mode value at reset nominal value 0x1722 r 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved rxfifogethres hold txempty rxempty txoverflow rxoverflow rxoverflow when spi keeps on rece iving data and rx-fifo is full, the rxoverflow will be set to 1. txoverflow when 8032 writing data is fast than spi transmitting rate, the tx-fifo wi ll overflow indicated by txoverflow bit. rxempty indicate the tx-fifo is currently empty. txempty indicate the tx-fifo is currently empty. rxfifogethreshold when rx-fifo reach to rxdept h_intr (0x1721[3:0]), the rxfifogethreshold will se t to 1. 15.1.4 spi interrupt enable address access mode value at reset nominal value 0x1723 r/w 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved rxint txempty reserved txoverflow rxoverflow according to 0x1722, these interrupts will occur if the corresponding interrupts enable. rxoverflow rx overflow interrupt enable . txoverflow tx overflow interrupt enable . txempty tx empty interrupt enable. (recommended this bit served in low data rate inter face application.) rxint rx interrupt enable. r x interrupt occurs upon the number of rx data reach es rxdepth_intr[3:0]. 15.1.5 dumpbyte address access mode value at reset nominal value 0x1724 r 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dumpbyte[7:0] if 1720[3] dumpcmp is set to "1", the received byte will be filtered out (no write to rx-fifo) when du mpbyte is equal to received byte. 15.1.6 write tx fifo address access mode value at reset nominal value 0x1725 w 00 W681307 publication release date: may, 2007 revision 1.3 - 130 - bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 txfifo[7:0] store data in spi tx-fifo when micro controller wri tes data to this register. 15.1.7 read rx fifo address access mode value at reset nominal value 0x1726 r 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rxfifo[7:0] read data from spi rx-fifo when micro controller re ad data from this register. 15.1.8 spi_transfer_size address access mode value at reset nominal value 0x1727 r/w 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved transfer size [3:0] spi_transfer_size perform (transfer size+1 ) bytes of tx/rx when start_rtx is set. ( master mode only) 15.1.9 spi_start_rtx address access mode value at reset nominal value 0x1728 r/w 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved reserved reserved reserved start_rtx start_rtx set to 1 to start tx/rx for (tra nsfer size+1) bytes; cleared by hardware automatica lly when it is done. ( master mode only ) W681307 publication release date: may, 2007 revision 1.3 - 131 - 16. spi for serial data flash 16.1 introduction to spi of serial data flash winbond W681307 chip embed a spi of serial data fla sh (df_spi) port which is a 4-pin (sck, /df_cs, sdi , sdo) spi interface. this spi interface makes W681307 chip easy to control 4- pin serial peripheral interface (spi) data flash me mories. it has various clock speed and data format configurations by setting control r egister. the spi interface can be operated at clock rates of up to cpu clk frequency / 2. 16.2 block diagram figure 16-1 the spi of the serial data flash bloc k diagram W681307 publication release date: may, 2007 revision 1.3 - 132 - 16.3 data format the packet/page data format is separated to 2 field s. first one is the command field, and the second o ne is data field. command field (1 ~ 5 bytes) is used to send the control instruction/ code and access address. the data field (0 ~ 256 by tes) is used to send/store the write/read data of serial data flash. all of comman d and data bytes are sand msb first. example 1: single byte command only example 2: multiple bytes command only example 3: sing le byte command with single byte write data example 4: single byte command with single byte rea d data W681307 publication release date: may, 2007 revision 1.3 - 133 - example 5: single byte command with multiple bytes write data example 6: single byte command with multiple bytes read data example 7: multip le bytes command with multiple bytes write data example 8: multiple bytes command with multiple byt es read data both command and data field length can be program w ith write the cmd_len (reg 0x1731[2:0]) and data_le n (reg 0x1732[7:0]). the max command field length is 5 bytes. the max da ta field length is 256 bytes. W681307 publication release date: may, 2007 revision 1.3 - 134 - 16.4 fsm there have 3 states in the df_spi module : idle, cm d and data. step1. while power on reset, the fsm initial is in the idle state. step2. after enable the df_spi function (write reg 0x1730[7]=1), the fsm start to wait the cpu control to change to cmd state (write reg 0x1731), then force control logic to shift out the command bytes sequentially to serial data flash . step3. after finished shift out the command bytes, the fsm will change to data state if the data_enb ( reg 0x1731[4]) is true, or run back to idle state if the data_enb is false. step4. when fsm goes into data state, the control l ogic will start to shift out the write out data to serial data flash if df_rd (reg 0x1731[3]) is false, or shift in the read back data from serial data flash if df_rd (reg 0x1731[3]) if true. step5. after finished shift out/in the data bytes, the fsm will go back to idle state, and wait for ne xt transition. 16.5 fifo/ram the df_spi module takes 5 bytes register to write t he control command and takes the 256x8 bytes ram to do the read/write access fifo. it supports 2 kinds of memory access method type1. fifo like method: the cpu always read/write the same address, then th e hardware control the memory read/write address, a nd increase the read/write point automatically after each read/writ e. the current write/read point can be read back at reg 0x173e/0x173f. type2. direct access method: the cpu can read/write any byte of the memory with write the read (reg 0x173f)/write (reg 0x173e) poin t first. 16.6 interrupt the df_spi module supports two kinds of interrupt s ource. one is the tx/rx finish interrupt, occur whi le tx/rx byte counts (reg 0x173d) is equal to data_len, the other is middle f lag interrupt, occur while tx/rx byte counts (reg 0 x173d) is equal to the 16 * intr_cnt (reg 0x1733[7:4]). any other concept, plea se reference to the description of the registers. 16.7 df_spi register group 16.7.1 df_clk address access mode value at reset nominal value 0x1730 r/w 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 df_enb clk_reg [6:0] clk_reg clock divider base to decide the df_clk clock frequ ency. df_clk freq. = cpu clk freq. / (clk_reg + 1) ex: clk_reg [6:0] = 0x01 df_clk freq. = cpu clk freq. / 2 clk_reg [6:0] = 0x03 df_clk freq. = cpu clk freq. / 4 note: clk_reg [6:0] must 1 while df_clk active. R RR R W681307 publication release date: may, 2007 revision 1.3 - 135 - df_enb when set, enable df_spi module. when reset, disable df_spi module. note: the fifo/ram only can be access while this bi t is set enable. 16.7.2 df_cmd_len address access mode value at reset nominal value 0x1731 r/w 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 data_enb df_rd cmd_len [2:0] cmd_len command field length. (unit: byte,cmd_len Q 4 ) command field length = cmd_len + 1 ex: cmd_len = 0x03 command field length = 4 bytes. df_rd read/write flag. (1: read,0: write) data_enb enable data field. (1: enable, 0: disable ) note: while df_enb = 1, write this byte will force df module start to tx/rx 16.7.3 df_data_len address access mode value at reset nominal value 0x1732 r/w 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 data_len [7:0] data_len data field length.(unit: byte) data field length = data_len + 1 ex: data_len = 0x0f data field length = 16 bytes. 16.7.4 df_intr_reg address access mode value at reset nominal value 0x1733 r/w 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 intr_cnt [3:0] rd_flag rx_ok tx_ok intr_enb intr_enb when set, enable df module interrupt. when reset, disable df module interrupt. this module support 2 kind of interrupt source. one is the tx/rx finished interrupt (occurred while tx/rx bytes = data_len), the other is internal pre-interrupt (occurred while tx/rx bytes = intr_cnt * 16). tx_ok tx finish interrupt.( read only) this bit will be clear automatically while next tx/ rx W681307 publication release date: may, 2007 revision 1.3 - 136 - rx_ok rx finish interrupt.( read only) this bit will be clear automatically while next tx/ rx rd_flag the same with df_rd. ( read only) intr_cnt internal pre interrupt. internal interrupt @ tx/rx byte count = (intr_cnt * 16). if want to disable the internal pre-interrupt, plea se set intr_cnt = 0 while internal pre-interrupt occurred, the interrup t status tx_ok/rx_ok will be both zero. the rd_flag will indicate the pre-interrupt i s tx or rx. ex:intr_cnt [3:0] = 0x01 internal interrupt @ tx/rx = byte 16. 16.7.5 df_cmd_b1 ~ df_cmd b5 address access mode value at reset nominal value 0x1734 r/w 00 address access mode value at reset nominal value 0x1735 r/w 00 address access mode value at reset nominal value 0x1736 r/w 00 address access mode value at reset nominal value 0x1737 r/w 00 address access mode value at reset nominal value 0x1738 r/w 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cmd_b1 [7:0] cmd_b2 [7:0] cmd_b3 [7:0] cmd_b4 [7:0] cmd_b5 [7:0] cmd_b1 command byte 1.(0x1734) cmd_b2 command byte 2.(0x1735) cmd_b3 command byte 3.(0x1736) cmd_b4 command byte 4.(0x1737) cmd_b5 command byte 5.(0x1738) W681307 publication release date: may, 2007 revision 1.3 - 137 - 16.7.6 df_clk_format address access mode value at reset nominal value 0x173b r/w 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 csn_more ck_more cp ci there have 4 control bits (csn_more, ck_more, cp an d ci) to decide the df_spi data format. csn_more when set, df_csn toggling only while df_clk stable. ck_more extend one more clock before/after signal df_csn ac tive. cp df_clk transition position setting. when cp = 1, df_clk start toggling in the middle of transfer. when cp = 0, df_clk start toggling at the beginning of transfer. ci df_clk level while df_csn is non active. when ci = 1, df_clk is high while df_csn is non act ive. when ci = 0, df_clk is low while df_csn is non acti ve. csn_more when set, df_csn toggling only while df_cl k stable. ck_more extend one more clock before/after signal d f_csn active. cp df_clk transition position setting. -- when cp = 1, df_clk start toggling in the middle of transfer. -- when cp = 0, df_clk start toggling at the beginn ing of transfer. W681307 publication release date: may, 2007 revision 1.3 - 138 - ci df_clk level while df_csn is non active -- when ci = 1, df_clk is high while df_csn is non active. -- when ci = 0, df_clk is low while df_csn is non a ctive. note: for w25x and w25p serial spi-flash, these con trol bits are all zeros. 16.7.7 df_fifo_data address access mode value at reset nominal value 0x173c r/w 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 fifo_data [7:0] fifo_data tx/rx fifo read/write data. when write this byte, i.e. put transmit data into f ifo. when read this byte, i.e. read back the current dat a in fifo. after read/write this byte, the cpu read/write poin t will increase one automatically. 16.7.8 df_cnt address access mode value at reset nominal value 0x173d r 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 df_cnt [7:0] df_cnt current tx/rx byte count point. W681307 publication release date: may, 2007 revision 1.3 - 139 - 16.7.9 df_wr_cnt address access mode value at reset nominal value 0x173e r/w 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 df_wr_cnt [7:0] df_wr_cnt cpu current write-point. (unit: byte) write this byte will force cpu write point set to t he df_wr_cnt value . 16.7.10 df_rd_cnt address access mode value at reset nominal value 0x173f r/w 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 df_rd_cnt [7:0] df_rd_cnt cpu current read-point. (unit: byte) write this byte will force cpu read point set to th e df_rd_cnt value. 16.8 example of w25x20/40/80 serial flash 1. write enable(0x1734 = 06) / write disable(0x1734 = 04) / chip erase(0x1734 = c7) / power-down(0x1734 = b9) 0x1730 = 0x81// set df_enb, clk = cpu clock / 2 0x1734 = 0x06// set cmd byte1 0x06 / 0x04 / 0xc7 / 0xb9 (code) 0x1731 = 0x00// force 1 byte tx (cmd) 2. read status register(0x1734 = 05) 0x1730 = 0x87// set df_enb, clk = cpu clock / 8 0x1732 = 0x00// set cmd data field length = 1 byte 0x1734 = 0x05// set byte1 0x05 (code) 0x1731 = 0x18// force 1 byte tx (cmd), and 1 byte r x 3. write status register(0x1734 = 01) 0x1730 = 0x8a// set df_enb, clk = cpu clock / 11 0x1734 = 0x01// set cmd byte1 0x01 (code) 0x1735 = 0x04// set cmd byte2 0x04 (s7-s0) 0x1731 = 0x01// force 2 bytes tx (cmd) 4. block erase(0x1734 = d8) / sector erase(0x1734 = 20 ) 0x1730 = 0x8a// set df_enb, clk = cpu clock / 11 0x1734 = 0xd8// set cmd byte1 0xd8 / 0x20 (code) 0x1735 = 0x34// set cmd byte2 0x34 (a23-a16) 0x1736 = 0x35// set cmd byte3 0x35 (a15-a8) 0x1737 = 0x36// set cmd byte4 0x36 (a7-a0) 0x1731 = 0x03// force 4 bytes tx (cmd) W681307 publication release date: may, 2007 revision 1.3 - 140 - 5. read data (0x1734 = 03) 0x1730 = 0x8b// set df_enb, clk = cpu clock / 12 0x1732 = 0x0f// set data field length = 16 bytes 0x1733 = 0x01// enable interrupt 0x1734 = 0x03// set cmd byte1 0x03 (code) 0x1735 = 0x04// set cmd byte2 0x04 (a23-a16) 0x1736 = 0x05// set cmd byte3 0x05 (a15-a8) 0x1737 = 0x06// set cmd byte4 0x06 (a7-a0) 0x1731 = 0x1b// force 4 bytes tx (cmd), and 16 byte s rx (data) 6. page program (0x1734 = 02) 0x1730 = 0x83// set df_enb, clk = cpu clock / 4 0x1732 = 0x0f// set data field length = 16 bytes 0x1734 = 0x02// set cmd byte1 0x02 (code) 0x1735 = 0x52// set cmd byte2 0x54 (a23-a16) 0x1736 = 0x51// set cmd byte3 0x55 (a15-a8) 0x1737 = 0x50// set cmd byte4 0x56 (a7-a0) 0x173e = 0x00// reset cpu write point to 0x00 0x173c = 0xd0// write data byte 1 (first data byte) 0x173c = 0xdf// write data byte 16 (last data byte) 0x1731 = 0x13// force 4 bytes tx (cmd), and 16 byte s tx (data) 7. release power-down and device id (0x1734 = ab) 0x1730 = 0x84// set df_enb, clk = cpu clock / 5 0x1732 = 0x00// set data field length = 1 bytes 0x1734 = 0xab// set cmd byte1 0xab (code) 0x1735 = 0x00// set cmd byte2 0x00 (dummy) 0x1736 = 0x00// set cmd byte3 0x00 (dummy) 0x1737 = 0x00// set cmd byte4 0x00 (dummy) 0x1731 = 0x1b// force 4 bytes tx (cmd), and 1 byte rx (data) 8. manufacturer-device id(0x1734 = 90) 0x1730 = 0x85// set df_enb, clk = cpu clock / 6 0x1732 = 0x01// set data field length = 2 bytes 0x1734 = 0x90// set cmd byte1 0x90 (code) 0x1735 = 0x00// set cmd byte2 0x00 (dummy) 0x1736 = 0x00// set cmd byte3 0x00 (dummy) 0x1737 = 0x00// set cmd byte4 0x00 (00h) 0x1731 = 0x1b// force 4 bytes tx (cmd), and 2 bytes rx (data) 9. jedecid(0x1734 = 9f) 0x1730 = 0x85// set df_enb, clk = cpu clock / 6 0x1732 = 0x02// set data field length = 3 bytes 0x1734 = 0x9f// set cmd byte1 0x9f (code) 0x1731 = 0x18// force 1 bytes tx (cmd), and 3 bytes rx (data) W681307 publication release date: may, 2007 revision 1.3 - 141 - 17. winbond 2-wire serial bus 17.1 introduction to winbond 2-wire serial bus winbond 2-wire serial bus (w2s) is a simple bi-dire ctional 2-wire bus for efficient inter-ic control. this design is for w2s master use only, and governed by micro controller, typically a n 8032. the w2s used in the chip is used to both re ad/write from/to eeprom and control melody device. the w2s master controller eq uips 35 bytes fifo performing w2s formatting and de -formatting. the micro controller can simply fill up the fifo contents whi ch consists of target device id, high/low address ( depend on the device format); for reading, just set read enable , for writing, keep w riting data to fifo then set write enable to launch transmission. the w2s master controller supports up to 3 kinds of page writing, i.e. 8, 16, 32 bytes. the w2s master controller des igned to support maximum 32 bytes per page, and the fifo depth is calculated as 3 hea der bytes (one device id, two address) plus 32 byte s for data. it has various bus speed configurations to support wide range of eeprom bus speed. 17.2 the description of w2s register 17.2.1 w2s_enable address access mode value at reset nominal value 0x1740 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w2s_ena w2s_port_sel reserved reserved reserved reserved reserved w2s_hw _protection w2s_ena: set this bit will activate w2s bus control ler. w2s_port_sel: pin selection for hardware w2s bus fu nction. w2s_port_sel pin name 0 p1.2 : sda0 p1.3 : scl0 1 p1.3 : sda1 p1.4 : scl1 if w2s_hw_protection is set to 1, the couple of pi ns set by bit w2s_port_sel become tri-state as core power below the operation voltage (see following table). micro -c must set w2s_ena bit before setup force_activity (0x1745) register, and the content of w2s status ( 0x1746) is valid only if w2s_ena bits is set to 1. w2s_hw_protection: set this bit will force w2s bus pins into tri-state output mode, when the cpwr_det is low activity. which pins will be forced to tri-state output is dependent on the w2s_ena and w2s_port_sel bits setting. the forc ed pins are listed as below when the bit cpwr_det is low. that means the core power voltage is below 1.7v. and the hardware w2s bus wil l into protection mode to avoid the e2prom data corruption. table 17-1 cpwr_det (read only) 0 1 w2s_hw_protection 0 1 don?t care w2s_ena x don?t care don?t care w2s_port_sel x 0 1 don?t care p1.2 x v x x p1.3 x v v x p1.4 x x v x ps v means this pin is forced to tri-state output mode . x means this pin state no any change. W681307 publication release date: may, 2007 revision 1.3 - 142 - 17.2.2 eeprom_config address access mode value at reset nominal value 0x1741 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved reserved eeprom_format header this register is used for w2s bus read cycle. eeprom_format is used for different page mode: eeprom_format page mode 0 0 8-byte 0 1 16-byte 1 0 32-byte 1 1 reserved header bit is used to support different page size o f eeprom. ?0? is for c16, ?1? is for c32/64/128/256 17.2.3 prescale_lo address access mode value at reset nominal value 0x1742 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 prescale_lo this register is used to control w2s bus speed, com panion with prescale_hi register. for 100khz w2s bus operation, set prescale_lo to 22 h, and prescale_hi to 00h. 17.2.4 prescale_hi address access mode value at reset nominal value 0x1743 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 prescale_hi this register is used to control w2s bus speed, com panion with prescale_lo register. for 100khz w2s bus operation, set prescale_lo to 22 h, and prescale_hi to 00h. prescale reg. value w2s bus clock 0x0068 33 khz 0x0034 66 khz 0x0022 100 khz 0x0019 133 khz 0x0014 166 khz 0x0006 500 khz system clock: 13.824 mhz ( ) 1 prescale 4 clock system clock bus w2s + = W681307 publication release date: may, 2007 revision 1.3 - 143 - 17.2.5 rdwrfifo address access mode value at reset nominal value 0x1744 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 8-bit data from/to fifo this register can be used for w2s both read and wri te w2s-bus compatible device. writing data (including target device id, high addr ess, low address, and repeat id, data) to this regi ster will be automatically stored in w2s controller fifo. when micro-c receives interrup t from w2s, micro-c need to check w2sstatus (0x1746 ) register to confirm the transmission is ok. if there is no error during w2s read process, micro-c can start reading fifo conte nt by reading rdwrfifo register. micro -c must set rdactive bit (0x1745[5]) before start r eading rdwrfifo (0x1744) w2s fifo content. 17.2.6 force_activity address access mode value at reset nominal value 0x1745 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved rdactive reserved rst_rd_ptr rst_wr_ptr rdwrn rdwr_en rdactive: set rdactive bit will enable the read cap ability of rdwrfifo (0x1744). to achieve stop pattern on w2s bus at power on init ial, it can send ?acknowledge polling? pattern. how to send ?acknowledge polling? pattern: after bit w2s_ena (of register 1470) set 1, writes 0x00h or 0xa0h to fifo (0x1744h). finally, sets force_activity (0x17 45) to 0x01h. after these operations, w2c controller can start re ading from or writing to eeprom. this mechanism use d for once when power on is an option to enhance eeprom stability. set rst_rd_ptr bit will rest w2s controller interna l fifo read pointer. set rst_wr_ptr bit will rest w2s controller interna l fifo write pointer. rdwrn: for read operation, reset rdwrn to 0, for wr ite operation, set rdwrn to 1. set rdwr_en bit will enable read or write operation depend on rdwrn. micro -c must set w2s_ena bit before setup force_activity . write 0xff to 0x1746 to reset all w2s_status bits and reset w2s -fifo both read and write pointer (0x1745[3] and 0x 1745[2] set to 1) and then clear (0x1745[3] and 0x1745[2] reset to 0) before enable read or write operation. 17.2.7 w2s_status address access mode value at reset nominal value 0x1746 r 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved reserved fifo_empty fifo_full ack_fail fifo_empty bit will generate w2s interrupt during w rite operation. fifo_full bit will generate w2s interrupt during re ad operation. ack_fail bit indicates that there is no response fo r target device during ack period rread or write pr ocess, this bit will generate w2s interrupt. w2s_status register content is valid only if w2s_en a bit has been set. W681307 publication release date: may, 2007 revision 1.3 - 144 - 17.2.8 fifordptr address access mode value at reset nominal value 0x1747 r 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved fifordptr this register is used to monitor w2s fifo read poin ter. 17.2.9 fifowrptr address access mode value at reset nominal value 0x1748 r 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved fifowrptr this register is used to monitor w2s fifo write poi nter. 17.2.10 forceackfail address access mode value at reset nominal value 0x1749 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ackfailena reserved ackfailptr ackfailena: enable ack fail event ackfailptr: during write data to eeprom or melody d evices, the ack fail event will occur at the ackfai lptr-th data of w2s fifo content. 17.2.11 w2s_misc address access mode value at reset nominal value 0x174a r 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved scl_in c_state w2sintrpt this register only monitor several status. scl_in: 0: current scl_in is pull low, 1: current s cl_in pull high. c_state: current finite state machine state. w2sintrpt: current interrupt signal indication. W681307 publication release date: may, 2007 revision 1.3 - 145 - 18. usb device controller and transceiver 18.1 overview w9681307 is built in a fully functional usb 1.1 con troller to be an usb device. it supports most funct ions of usb 1.1 standard specification and some required functions of usb au dio class and hid class profiles for driver free on microsoft os in skype or voip wireless applications. in isp mode application, use rs also can download program code between pc and ex ternal rom flash memory via usb now. the usb core embeds one 512x8 byte rom to store default descriptors. in the setting, the usb core includes four interfaces and seven endpoints to handle above applications. 18.2 functionality figure 18-1 the usb block diagram the usb block diagram is shown in figure 18-1. the usb module supports all transfer types (control end point 0, bulk in, bulk out, interrupt in, isochronous in, and isochronous out) in. usb 1.1 spec and W681307 usb embeds seven endpo ints include control endpoint 0. the default descriptors are stored in t he 512x8 bytes rom. the sie module is for handle us b series-interface-engine functions. ucom module is a bridge to communicate s ie and all transfer type modules. register control module is for handle cpu read/write and data signals of W681307 usb register s. gain stage is required for adjust gain of pcm da ta in audio volume control application. usb test module connects many internal signals to test pins for help monitor them from ou tside. the feature of the usb module is as follows usb specification version 1.1 compliant full-speed (12mhz) audio class interface and command support (volume c ontrol, mute control) hid class interface and command support (set report ) usb isp mode support vendor command support programmable to connect/disconnect 1.5kohm pull-up resistance on d+ bus support five interfaces and seven endpoints (contro l, bulk in, bulk out, interrupt in, isochronous in, and isochronous out) ping-pong fifo control for bulk in/bulk out transfe r to get better performance provide one of three bytes isochronous in endpoint to synchronize isochronous out endpoint for let pc trim the speed of data stream to improve voice quality. W681307 publication release date: may, 2007 revision 1.3 - 146 - mass storage class command support (ger_max_lun) 18.2.1 endpoints the definitions of embedded endpoints are in table 18-1. address type direction maximum packet size (bytes) memory type 0 control in/out 8 registers 1 iso in 16 2 iso out 18 64x16 (shared ? double buffer) 3 bulk in 64 128 x 8 (double buffer) 4 bulk out 64 128 x 8 (double buffer) 5 interrupt in 8 registers 6 iso in 3 registers table 18-1 W681307 usb endpoint definitions 18.2.2 descriptor rom the default descriptors are stored in the 512x8 byt es rom. the address mapping and bank definition of this rom are shown in figure 18-2. the logical topology from these descriptors i s shown in figure 18-3. 0x000h ~ 0x011h device descriptor 18 bytes 0x012h ~ 0x17fh configuration descriptor + interface descriptor + endpoint descriptor + audio class descriptor + hid descriptor + report descriptor 366 bytes 0x180h ~ 0x183h string descriptor index 0 4 bytes 0x184h ~ 0x1bfh string descriptor index 1 60 bytes 0x1c0h ~ 0x1dfh string descriptor index 2 32 bytes 0x1e0h ~ 0x1ffh string descriptor index 3 32 bytes figure 18-2 descriptor rom definitions W681307 publication release date: may, 2007 revision 1.3 - 147 - figure 18-3 the local topology of embedded descri ptors 18.2.3 configurations and interfaces the configuration and interface settings in W681307 usb are shown in figure 18-3. the descriptions are as follows configuration 0 : the default configuration for all usb devices interface 0 : the default interface for all usb dev ices configuration 1 interface 0 : audio class interface interface 1 : audio class interface for record mode alternate 0 : record off alternate 1 : record on interface 2 : audio class interface for play mode alternate 0 : play off alternate 1 : play on interface 3 : hid class interface for commands/stat us communications interface 4 : non-class interface for usb isp mode or mass data transfer W681307 publication release date: may, 2007 revision 1.3 - 148 - 18.2.4 audio class W681307 usb provides audio class interfaces so it d oes not need extra driver to be an usb audio device in microsoft o/s (windows 2000/xp). figure 18-4 is shown an usb audio class d evice topology from embedded descriptors. figure 18-4 usb audio class device topology W681307 usb implements volume control and mute cont rol in play and record modes. 18.2.4.1 play mode we define the play mode as the traffic flows from t he host to the usb device and to the baseband. the host can turn on/off the play mode by setting the alternative value from set interface 2 command. 18.2.4.2 record mode define the record mode as the traffic flows from th e baseband to the usb host. the host can turn on/of f the record mode by setting the alternative value from set interface 1 command. 18.2.4.3 mute control the host can issue set_cur command with wvalue equa ls to 0x100 to change the mute function of the usb device. the host can turn on/off the mute as requests by the users. if the ho st selects feature unit number 1 (id is 3), the mut e of audio stream from mic to usb is changed; if the host selects feature unit number 2 (id is 6), the mute of audio stream from usb to spe aker is updated. the host also can issue get_cur command to read back current mute sta tus. play mode record mode play data to baseband record data to host on on if play mute is on, send 16?h0000; otherwise same as data from host if record mute is on, send 16?h0000; otherwise same as data from baseband on off if play mute is on, send 16?h0000; otherwise same as data from host no data to host off on 16?h0000 if record mute is on, send 16?h0000; otherwise same as data from baseband off off 16?h0000 no data to host audio function ot ot it it id1 id4 id3 id2 id6 id5 mic speaker usb streaming usb streaming iso out (ep2) (usb out) (usb in) iso in (ep1) iso in (ep6) interface 1 (alternate 1) interface 2 (alternate 1) W681307 publication release date: may, 2007 revision 1.3 - 149 - play mute on/off means set_cur for mute control and feature unit id 6 then received data = 1/0 record mute on/off means set_cur for mute control a nd feature unit id 3 then received data = 1/0 18.2.4.4 volume control the host can issue set_cur commands with wvalue equ als to 0x0200 to change the volumes of the usb devi ce. if the host selects feature unit number 1 (id is 3), the volume of audi o stream from mic to usb (means record volume) is c hanged; if the host selects feature unit number 2 (id is 6), the volume of audi o stream from usb to speaker (means play volume) is updated. the host also can issue get_cur command to read back current volume g ain value. data settings & gain mapping play data to baseband record data to host 0x7fff ? 0x18xx 0x17xx ? 0x01xx 0x00xx 0xffxx 0xfexx ? 0xe2xx 0xe1xx ? 0x8000 +24 db +24 db +24 db +23 db ? +1 db 0 db -1 db -2 db ? -29 db -30 db -30 db -30 db if host sends set_cur for volume control in play path, device will adjust gain of pcm_tx[15:0] via the command then enter baseband after leave iso out fifo if host sends set_cur for volume control in record path, device will adjust gain of pcm_rx[15:0] via the command then enter iso in fifo the default value of get_cur for volume control is 0x0000 (0 db) get_min is 0xe100 (-30db), get_max is 0x1800 (+24 d b) and get_res is 0x0100 (+1 db) 18.2.4.5 synchronization for data transfer to better synchronization, an endpoint (endpoint 6) is dedicated to provide rate adjustment informatio n to host. the descriptor can set a time interval, so the host will request the rate in formation (3 bytes) from that endpoint by using tha t frequency. 18.2.4.6 audio data format the data format is 16 bits linear pcm in audio path and the sample frequency is 8 khz. 18.2.5 hid class interface 3 is a hid class interface and it has one interrupt in endpoint. the device can receive comm ands from host via set report and report hardware?s status to host via interrupt in transfer in skype application. 18.2.5.1 set (feature) report i n default descriptors, define 8 bytes feature repor t descriptors in report descriptor. host can send s et report command to device then the device can do the action after receive and anal yze these 8 bytes data. we use the way to deliver s kype or winbond commands from host to device. 18.2.5.2 interrupt in we use the interrupt in transfer to report the devi ce status to host. the maximum packet size is 8 byt es and the time of polling interval is about 64 ms. W681307 publication release date: may, 2007 revision 1.3 - 150 - 18.2.6 usb isp mode interface 4 does not belong to any class. it has on e bulk in and bulk out endpoints. both maximum pack et sizes are 64 bytes. for gain better performance, we implement ping-pong fifo con trol in bulk in/out transfer. usb isp mode uses interface 4. it can download code from pc to external flash by bulk out or read the code of external flash on pc by bulk in via usb bus after install the driver. 18.2.7 vendor command the vendor command is supported. the bits [6:5] = 2 means vendor command and bit 7 means data transfer direction in byte 0 of setup data in usb 1.1 spec. based on the rules, use rs can define individual vendor commands and use th em to communicate host and device. 18.3 usb registers 18.3.1 usb enable register address access mode value at reset nominal value 0x1800 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved se0_dis r_pullup trx_en pll_en suspend_en usb_reset usb_rese active high. reset usb digital par t. and when s/w receive reset interrupt (from host) , could use this bit to reset usb. suspend_en active high. active high and disable the bias current of transceiver. pll_en active high. enable charge pump a nd vco. trx_en active high. enable transceiver. r_pullup active high. enable a pull-up res ister (1.5k ohm) to d+. se0_dis active high, disable se0. defaul t is low, and set d+ and d- to ?0?. when usb device need to enable a pull-up resister t o d+, it also need to disable se0 state. 18.3.2 usb interrupt register a 18.3.2.1 enable address access mode value at reset nominal value 0x1801 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 set_hid _intrpt reserved cdi_intrpt cdo_intrpt irqi_intrpt bko_intrpt bki_intrpt vender _intrpt 18.3.2.2 status address access mode value at reset nominal value 0x1802 r 0x00 W681307 publication release date: may, 2007 revision 1.3 - 151 - bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 set_hid _intrpt reserved cdi_intrpt cdo_intrpt irqi_intrpt bko_intrpt bki_intrpt vender _intrpt 18.3.2.3 clear address access mode value at reset nominal value 0x1803 w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 set_hid _intrpt reserved cdi_intrpt cdo_intrpt irqi_intrpt bko_intrpt bki_intrpt vender _intrpt vender_intrpt detection of vender request bki_intrpt detection of bulk in(ep 3) request bko_intrpt detection of bulk out(ep4 ) request irqi_intrpt detection of interrupt i n(ep5) request cdo_intrpt detection of control out (ep0) request cdi_intrpt detection of control in (ep0) request set_hid_intrpt detection of set hid report r equest 18.3.3 usb interrupt register b 18.3.3.1 enable address access mode value at reset nominal value 0x1804 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 playon _intrpt recordon _intrpt reserved connect _intrpt usb_error_i ntrpt host_resume_i ntrpt host_suspend _intrpt host_reset _intrpt 18.3.3.2 status address access mode value at reset nominal value 0x1805 r 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 playon _intrpt recordon _intrpt reserved connect _intrpt usb_error_i ntrpt host_resume_i ntrpt host_suspend_i ntrpt host_reset _intrpt W681307 publication release date: may, 2007 revision 1.3 - 152 - 18.3.3.3 clear address access mode value at reset nominal value 0x1806 w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 playon _intrpt recordon _intrpt reserved connect _intrpt usb_error _intrpt host_resume_i ntrpt host_suspend _intrpt host_reset _intrpt host_reset_intrpt detection of reset r equest. host_suspend_intrpt detection of suspend re quest host_resume_intrpt detection of resume req uest usb_error_intrpt detection of error req uest (ex: crc) connect_intrpt detection of connect recordon_intrpt detection of reco rd on playon_intrpt detection of p lay on 18.3.4 endpoint 0 ? control in/out registers 18.3.4.1 control register address access mode value at reset nominal value 0x1810 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved reserved hid_fifo _empty sdo_rd ctl_in_rdy ctl_in_rdy active high. control in(ep0 ) data is ready. s/w needs to set this bit when the y finished writing the control in data (max: 8 bytes) sdo_rd setup or data out pack et is reading for control transfer. hid_fifo_empty while s/w complete to read th e control hid out data (0x1820 ~0x1827), set ?hid_f ifo_empty? to high. usb device will send nak before ?hid_fifo_empty? settin g to high. 18.3.4.2 control in data address access mode value at reset nominal value 0x1811 w/r 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ctli_d [7:0] ctli_d control in data. internal fifo has 8 bytes. W681307 publication release date: may, 2007 revision 1.3 - 153 - 18.3.4.3 control hid out data address access mode value at reset nominal value 0x1820 ~ 0x1827 r 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ctlo_hid0 [7:0] ~ ctlo_hid7 [7:0] 18.3.4.4 control out data address access mode value at reset nominal value 0x1828 ~ 0x182f r 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ctlo_d0 [7:0] ~ ctlo_d7 [7:0] 18.3.5 endpoint 1 and 2 ? iso in/out registers 18.3.5.1 control register address access mode value at reset nominal value 0x1830 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved reserved reserved iso_en iso_rst iso_rst active high reset iso in/out function iso_en active high, enables iso in/out func tion. 18.3.5.2 iso sync speed register address access mode value at reset nominal value 0x1838~0x1839 r/w 0xffc0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 iso_sync_speed_0[15:8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 iso_sync_speed_0[7:0] W681307 publication release date: may, 2007 revision 1.3 - 154 - address access mode value at reset nominal value 0x183a~0x183b r/w 0xffe0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 iso_sync_speed_1[15:8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 iso_sync_speed_1[7:0] address access mode value at reset nominal value 0x183c~0x183d r/w 0xfff0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 iso_sync_speed_2[15:8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 iso_sync_speed_2[7:0] address access mode value at reset nominal value 0x183e~0x183f r/w 0xfffe bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 iso_sync_speed_3[15:8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 iso_sync_speed_3[7:0] address access mode value at reset nominal value 0x1840~0x1841 r/w 0x0002 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 iso_sync_speed_4[15:8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 iso_sync_speed_4[7:0] address access mode value at reset nominal value 0x1842~0x1843 r/w 0x0010 W681307 publication release date: may, 2007 revision 1.3 - 155 - bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 iso_sync_speed_5[15:8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 iso_sync_speed_5[7:0] address access mode value at reset nominal value 0x1844~0x1845 r/w 0x0020 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 iso_sync_speed_6[15:8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 iso_sync_speed_6[7:0] address access mode value at reset nominal value 0x1846~0x1847 r/w 0x0040 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 iso_sync_speed_7[15:8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 iso_sync_speed_7[7:0] 18.3.6 endpoint 3 ? bulk in registers 18.3.6.1 control register address access mode value at reset nominal value 0x1848 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved reserved reserved bki_en bki_rst bki_rst active high, reset bulk in function bki_en: active high, enable bulk in functi on. W681307 publication release date: may, 2007 revision 1.3 - 156 - 18.3.6.2 bulk in data address access mode value at reset nominal value 0x1849 w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bki_data[7:0] bki_data bulk_in data except final data. 18.3.6.3 bulk in final data address access mode value at reset nominal value 0x184a w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bki_eop_data[7:0] bki_eop_data bulk_in end of packet data. 18.3.6.4 bulk in fifo empty flag address access mode value at reset nominal value 0x184b r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved reserved reserved reserved bki_fifo _empty bki_fifo_empty fifo 0 or fifo 1 empty flag . s/w needs to check this bit to decide if there st ill had empty fifo to write. 18.3.7 endpoint 4 ? bulk out registers 18.3.7.1 control register address access mode value at reset nominal value 0x1850 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved reserved reserved bko_en bko_rst bko_rst active high, reset bulk out function bko_en active high, enable bulk out functio n W681307 publication release date: may, 2007 revision 1.3 - 157 - 18.3.7.2 bulk out fifo length address access mode value at reset nominal value 0x1851 r 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved bko_fifo_len[6:0] bko_fifo_len [6:0] it will show the presen t fifo length. 18.3.7.3 bulk out data address access mode value at reset nominal value 0x1852 r 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bko_d [ 7:0 ] bko_d bulk out data. 18.3.8 endpoint 5 ? interrupt in registers 18.3.8.1 control register address access mode value at reset nominal value 0x1858 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved reserved reserved irqi_en irqi_rst irqi_rst active high, reset irqi (ep5) functio n irqi_en active high, enable irqi (ep5) funct ion 18.3.8.2 usb interrupt data length address access mode value at reset nominal value 0x1859 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved irqi_start irqi_len [3:0] irqi_len [3:0] interrupt in (ep5) data leng th. irqi_start active high, interrupt i n (ep5) active. W681307 publication release date: may, 2007 revision 1.3 - 158 - 18.3.8.3 interrupt in data address access mode value at reset nominal value 0x1860 ~0x186f r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 irqi_d0 [7:0] ~ irqi_d15 [7:0] total 16 bytes interrupt in data. 18.3.9 specific register address access mode value at reset nominal value 0x1870 -1873 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 blocked (for test modes) 18.3.10 specific register address access mode value at reset nominal value 0x1874 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved reserved blocked (for test modes) blocked (for test modes) blocked (for test modes) 18.3.11 specific register address access mode value at reset nominal value 0x1875 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved reserved reserved reserved blocked (for test modes) W681307 publication release date: may, 2007 revision 1.3 - 159 - 19. package dimensions 100pin lqfp (14x14x1.4 mm footprint 2.0mm) controlling dimension : millimeters 0.10 0 7 0 0.004 1.00 0.75 0.60 0.45 0.039 0.030 0.024 0.018 0.638 0.630 0.622 0.50 14.10 0.20 0.27 1.45 1.60 14.00 1.40 13.90 0.10 0.17 1.35 0.05 0.008 0.011 0.057 0.063 0.055 0.020 0.556 0.551 0.547 0.004 0.007 0.053 0.002 symbol min nom max max nom min dimension in inch dimension in mm ab c d e h d h e ly a1 a 2 l1 e 0.009 0.006 0.15 0.22 7 13.90 14.00 14.10 15.80 16.00 16.20 15.80 16.00 16.20 0.556 0.551 0.547 ? 0.638 0.630 0.622 d d e e b a2 a1 a l1 e c l y h h 1 100 ? 25 26 50 51 7 5 7 6 W681307 publication release date: may, 2007 revision 1.3 - 160 - important notice winbond products are not designed, intended, author ized or warranted for use as components in systems or equipment intended for surgical implanta tion, atomic energy control instruments, airplane o r spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products f or use in such applications do so at their own risk and agree to fully indemnify winbond for any damage s resulting from such improper use or sales. |
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